linux/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
 */

#include "mdp5_kms.h"
#include "mdp5_ctl.h"

/*
 * CTL - MDP Control Pool Manager
 *
 * Controls are shared between all display interfaces.
 *
 * They are intended to be used for data path configuration.
 * The top level register programming describes the complete data path for
 * a specific data path ID - REG_MDP5_CTL_*(<id>, ...)
 *
 * Hardware capabilities determine the number of concurrent data paths
 *
 * In certain use cases (high-resolution dual pipe), one single CTL can be
 * shared across multiple CRTCs.
 */

#define CTL_STAT_BUSY …
#define CTL_STAT_BOOKED …

struct mdp5_ctl { … };

struct mdp5_ctl_manager { … };

static inline
struct mdp5_kms *get_kms(struct mdp5_ctl_manager *ctl_mgr)
{ … }

static inline
void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data)
{ … }

static inline
u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
{ … }

static void set_display_intf(struct mdp5_kms *mdp5_kms,
		struct mdp5_interface *intf)
{ … }

static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
{ … }

int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
{ … }

static bool start_signal_needed(struct mdp5_ctl *ctl,
				struct mdp5_pipeline *pipeline)
{ … }

/*
 * send_start_signal() - Overlay Processor Start Signal
 *
 * For a given control operation (display pipeline), a START signal needs to be
 * executed in order to kick off operation and activate all layers.
 * e.g.: DSI command mode, Writeback
 */
static void send_start_signal(struct mdp5_ctl *ctl)
{ … }

/**
 * mdp5_ctl_set_encoder_state() - set the encoder state
 *
 * @ctl:      the CTL instance
 * @pipeline: the encoder's INTF + MIXER configuration
 * @enabled:  true, when encoder is ready for data streaming; false, otherwise.
 *
 * Note:
 * This encoder state is needed to trigger START signal (data path kickoff).
 */
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
			       struct mdp5_pipeline *pipeline,
			       bool enabled)
{ … }

/*
 * Note:
 * CTL registers need to be flushed after calling this function
 * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
 */
int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
			int cursor_id, bool enable)
{ … }

static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
		enum mdp_mixer_stage_id stage)
{ … }

static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
		enum mdp_mixer_stage_id stage)
{ … }

static void mdp5_ctl_reset_blend_regs(struct mdp5_ctl *ctl)
{ … }

#define PIPE_LEFT …
#define PIPE_RIGHT …
int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
		   u32 stage_cnt, u32 ctl_blend_op_flags)
{ … }

u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)
{ … }

u32 mdp_ctl_flush_mask_cursor(int cursor_id)
{ … }

u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe)
{ … }

u32 mdp_ctl_flush_mask_lm(int lm)
{ … }

static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
			u32 flush_mask)
{ … }

static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
		u32 *flush_id)
{ … }

/**
 * mdp5_ctl_commit() - Register Flush
 *
 * @ctl:        the CTL instance
 * @pipeline:   the encoder's INTF + MIXER configuration
 * @flush_mask: bitmask of display controller hw blocks to flush
 * @start:      if true, immediately update flush registers and set START
 *              bit, otherwise accumulate flush_mask bits until we are
 *              ready to START
 *
 * The flush register is used to indicate several registers are all
 * programmed, and are safe to update to the back copy of the double
 * buffered registers.
 *
 * Some registers FLUSH bits are shared when the hardware does not have
 * dedicated bits for them; handling these is the job of fix_sw_flush().
 *
 * CTL registers need to be flushed in some circumstances; if that is the
 * case, some trigger bits will be present in both flush mask and
 * ctl->pending_ctl_trigger.
 *
 * Return H/W flushed bit mask.
 */
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
		    struct mdp5_pipeline *pipeline,
		    u32 flush_mask, bool start)
{ … }

u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
{ … }

int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
{ … }

/*
 * mdp5_ctl_pair() - Associate 2 booked CTLs for single FLUSH
 */
int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
{ … }

/*
 * mdp5_ctl_request() - CTL allocation
 *
 * Try to return booked CTL for @intf_num is 1 or 2, unbooked for other INTFs.
 * If no CTL is available in preferred category, allocate from the other one.
 *
 * @return fail if no CTL is available.
 */
struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
		int intf_num)
{ … }

void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctl_mgr)
{ … }

struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd)
{ … }