/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_MDSS_H #define _DPU_HW_MDSS_H #include <linux/kernel.h> #include <linux/err.h> #include "msm_drv.h" #include "disp/mdp_format.h" #define DPU_DBG_NAME … #define DPU_NONE … #ifndef DPU_CSC_MATRIX_COEFF_SIZE #define DPU_CSC_MATRIX_COEFF_SIZE … #endif #ifndef DPU_CSC_CLAMP_SIZE #define DPU_CSC_CLAMP_SIZE … #endif #ifndef DPU_CSC_BIAS_SIZE #define DPU_CSC_BIAS_SIZE … #endif #ifndef DPU_MAX_PLANES #define DPU_MAX_PLANES … #endif #define PIPES_PER_STAGE … #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES … #endif #define DPU_BLEND_FG_ALPHA_FG_CONST … #define DPU_BLEND_FG_ALPHA_BG_CONST … #define DPU_BLEND_FG_ALPHA_FG_PIXEL … #define DPU_BLEND_FG_ALPHA_BG_PIXEL … #define DPU_BLEND_FG_INV_ALPHA … #define DPU_BLEND_FG_MOD_ALPHA … #define DPU_BLEND_FG_INV_MOD_ALPHA … #define DPU_BLEND_FG_TRANSP_EN … #define DPU_BLEND_BG_ALPHA_FG_CONST … #define DPU_BLEND_BG_ALPHA_BG_CONST … #define DPU_BLEND_BG_ALPHA_FG_PIXEL … #define DPU_BLEND_BG_ALPHA_BG_PIXEL … #define DPU_BLEND_BG_INV_ALPHA … #define DPU_BLEND_BG_MOD_ALPHA … #define DPU_BLEND_BG_INV_MOD_ALPHA … #define DPU_BLEND_BG_TRANSP_EN … enum dpu_vsync_source { … }; enum dpu_hw_blk_type { … }; enum dpu_sspp { … }; enum dpu_sspp_type { … }; enum dpu_lm { … }; enum dpu_stage { … }; enum dpu_dspp { … }; enum dpu_ctl { … }; enum dpu_dsc { … }; enum dpu_cdm { … }; enum dpu_pingpong { … }; enum dpu_merge_3d { … }; enum dpu_intf { … }; /* * Historically these values correspond to the values written to the * DISP_INTF_SEL register, which had to programmed manually. On newer MDP * generations this register is NOP, but we keep the values for historical * reasons. */ enum dpu_intf_type { … }; enum dpu_intf_mode { … }; enum dpu_wb { … }; enum dpu_cwb { … }; enum dpu_wd_timer { … }; enum dpu_vbif { … }; /** * enum dpu_3d_blend_mode * Desribes how the 3d data is blended * @BLEND_3D_NONE : 3d blending not enabled * @BLEND_3D_FRAME_INT : Frame interleaving * @BLEND_3D_H_ROW_INT : Horizontal row interleaving * @BLEND_3D_V_ROW_INT : vertical row interleaving * @BLEND_3D_COL_INT : column interleaving * @BLEND_3D_MAX : */ enum dpu_3d_blend_mode { … }; /** * struct dpu_hw_fmt_layout - format information of the source pixel data * @format: pixel format parameters * @num_planes: number of planes (including meta data planes) * @width: image width * @height: image height * @total_size: total size in bytes * @plane_addr: address of each plane * @plane_size: length of each plane * @plane_pitch: pitch of each plane */ struct dpu_hw_fmt_layout { … }; struct dpu_csc_cfg { … }; /** * struct dpu_mdss_color - mdss color description * color 0 : green * color 1 : blue * color 2 : red * color 3 : alpha */ struct dpu_mdss_color { … }; /* * Define bit masks for h/w logging. */ #define DPU_DBG_MASK_NONE … #define DPU_DBG_MASK_INTF … #define DPU_DBG_MASK_LM … #define DPU_DBG_MASK_CTL … #define DPU_DBG_MASK_PINGPONG … #define DPU_DBG_MASK_SSPP … #define DPU_DBG_MASK_WB … #define DPU_DBG_MASK_TOP … #define DPU_DBG_MASK_VBIF … #define DPU_DBG_MASK_ROT … #define DPU_DBG_MASK_DSPP … #define DPU_DBG_MASK_DSC … #define DPU_DBG_MASK_CDM … /** * struct dpu_hw_tear_check - Struct contains parameters to configure * tear-effect module. This structure is used to configure tear-check * logic present either in ping-pong or in interface module. * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided * by no of lines * @sync_cfg_height: Total vertical lines (display height - 1) * @vsync_init_val: Init value to which the read pointer gets loaded at * vsync edge * @sync_threshold_start: Read pointer threshold start ROI for write operation * @sync_threshold_continue: The minimum number of lines the write pointer * needs to be above the read pointer * @start_pos: The position from which the start_threshold value is added * @rd_ptr_irq: The read pointer line at which interrupt has to be generated * @hw_vsync_mode: Sync with external frame sync input */ struct dpu_hw_tear_check { … }; /** * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure * read and write pointers for command mode panels * @rd_ptr_init_val: Value of rd pointer at vsync edge * @rd_ptr_frame_count: Num frames sent since enabling interface * @rd_ptr_line_count: Current line on panel (rd ptr) * @wr_ptr_line_count: Current line within pp fifo (wr ptr) * @intf_frame_count: Frames read from intf */ struct dpu_hw_pp_vsync_info { … }; #endif /* _DPU_HW_MDSS_H */
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