linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DPU_HW_CTL_H
#define _DPU_HW_CTL_H

#include "dpu_hw_mdss.h"
#include "dpu_hw_util.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_sspp.h"

/**
 * dpu_ctl_mode_sel: Interface mode selection
 * DPU_CTL_MODE_SEL_VID:    Video mode interface
 * DPU_CTL_MODE_SEL_CMD:    Command mode interface
 */
enum dpu_ctl_mode_sel { … };

struct dpu_hw_ctl;
/**
 * struct dpu_hw_stage_cfg - blending stage cfg
 * @stage : SSPP_ID at each stage
 * @multirect_index: index of the rectangle of SSPP.
 */
struct dpu_hw_stage_cfg { … };

/**
 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
 * @intf :                 Interface id
 * @mode_3d:               3d mux configuration
 * @merge_3d:              3d merge block used
 * @intf_mode_sel:         Interface mode, cmd / vid
 * @cdm:                   CDM block used
 * @stream_sel:            Stream selection for multi-stream interfaces
 * @dsc:                   DSC BIT masks used
 */
struct dpu_hw_intf_cfg { … };

/**
 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
 * Assumption is these functions will be called after clocks are enabled
 */
struct dpu_hw_ctl_ops { … };

/**
 * struct dpu_hw_ctl : CTL PATH driver object
 * @base: hardware block base structure
 * @hw: block register map object
 * @idx: control path index
 * @caps: control path capabilities
 * @mixer_count: number of mixers
 * @mixer_hw_caps: mixer hardware capabilities
 * @pending_flush_mask: storage for pending ctl_flush managed via ops
 * @pending_intf_flush_mask: pending INTF flush
 * @pending_wb_flush_mask: pending WB flush
 * @pending_dsc_flush_mask: pending DSC flush
 * @pending_cdm_flush_mask: pending CDM flush
 * @ops: operation list
 */
struct dpu_hw_ctl { … };

/**
 * dpu_hw_ctl - convert base object dpu_hw_base to container
 * @hw: Pointer to base hardware block
 * return: Pointer to hardware block container
 */
static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
{ … }

/**
 * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
 * Should be called before accessing any ctl_path register.
 * @dev:  Corresponding device for devres management
 * @cfg:  ctl_path catalog entry for which driver object is required
 * @addr: mapped register io address of MDP
 * @mixer_count: Number of mixers in @mixer
 * @mixer: Pointer to an array of Layer Mixers defined in the catalog
 */
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
				   const struct dpu_ctl_cfg *cfg,
				   void __iomem *addr,
				   u32 mixer_count,
				   const struct dpu_lm_cfg *mixer);

#endif /*_DPU_HW_CTL_H */