linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 */

#ifndef _DPU_HWIO_H
#define _DPU_HWIO_H

#include "dpu_hw_util.h"

/**
 * MDP TOP block Register and bit fields and defines
 */
#define DISP_INTF_SEL …
#define INTR_EN …
#define INTR_STATUS …
#define INTR_CLEAR …
#define INTR2_EN …
#define INTR2_STATUS …
#define SSPP_SPARE …
#define INTR2_CLEAR …
#define HIST_INTR_EN …
#define HIST_INTR_STATUS …
#define HIST_INTR_CLEAR …
#define SPLIT_DISPLAY_EN …
#define SPLIT_DISPLAY_UPPER_PIPE_CTRL …
#define DSPP_IGC_COLOR0_RAM_LUTN …
#define DSPP_IGC_COLOR1_RAM_LUTN …
#define DSPP_IGC_COLOR2_RAM_LUTN …
#define DANGER_STATUS …
#define SAFE_STATUS …
#define HW_EVENTS_CTL …
#define MDP_WD_TIMER_0_CTL …
#define MDP_WD_TIMER_0_CTL2 …
#define MDP_WD_TIMER_0_LOAD_VALUE …
#define MDP_WD_TIMER_1_CTL …
#define MDP_WD_TIMER_1_CTL2 …
#define MDP_WD_TIMER_1_LOAD_VALUE …
#define CLK_CTRL3 …
#define CLK_STATUS3 …
#define CLK_CTRL4 …
#define CLK_STATUS4 …
#define CLK_CTRL5 …
#define CLK_STATUS5 …
#define CLK_CTRL7 …
#define CLK_STATUS7 …
#define SPLIT_DISPLAY_LOWER_PIPE_CTRL …
#define SPLIT_DISPLAY_TE_LINE_INTERVAL …
#define INTF_SW_RESET_MASK …
#define HDMI_DP_CORE_SELECT …
#define MDP_OUT_CTL_0 …
#define MDP_VSYNC_SEL …
#define MDP_WD_TIMER_2_CTL …
#define MDP_WD_TIMER_2_CTL2 …
#define MDP_WD_TIMER_2_LOAD_VALUE …
#define MDP_WD_TIMER_3_CTL …
#define MDP_WD_TIMER_3_CTL2 …
#define MDP_WD_TIMER_3_LOAD_VALUE …
#define MDP_WD_TIMER_4_CTL …
#define MDP_WD_TIMER_4_CTL2 …
#define MDP_WD_TIMER_4_LOAD_VALUE …
#define DCE_SEL …

#define MDP_PERIPH_TOP0 …
#define MDP_PERIPH_TOP0_END …

#endif /*_DPU_HWIO_H */