linux/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
 */

#define pr_fmt(fmt) …
#include "dpu_encoder_phys.h"
#include "dpu_hw_interrupts.h"
#include "dpu_hw_merge3d.h"
#include "dpu_core_irq.h"
#include "dpu_formats.h"
#include "dpu_trace.h"
#include "disp/msm_disp_snapshot.h"

#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_managed.h>

#define DPU_DEBUG_VIDENC(e, fmt, ...) …

#define DPU_ERROR_VIDENC(e, fmt, ...) …

#define to_dpu_encoder_phys_vid(x) …

static bool dpu_encoder_phys_vid_is_master(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void drm_mode_to_intf_timing_params(
		const struct dpu_encoder_phys *phys_enc,
		const struct drm_display_mode *mode,
		struct dpu_hw_intf_timing_params *timing)
{ … }

static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
{ … }

static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
{ … }

/*
 * programmable_fetch_get_num_lines:
 *	Number of fetch lines in vertical front porch
 * @timing: Pointer to the intf timing information for the requested mode
 *
 * Returns the number of fetch lines in vertical front porch at which mdp
 * can start fetching the next frame.
 *
 * Number of needed prefetch lines is anything that cannot be absorbed in the
 * start of frame time (back porch + vsync pulse width).
 *
 * Some panels have very large VFP, however we only need a total number of
 * lines based on the chip worst case latencies.
 */
static u32 programmable_fetch_get_num_lines(
		struct dpu_encoder_phys *phys_enc,
		const struct dpu_hw_intf_timing_params *timing)
{ … }

/*
 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
 *	the start of fetch into the vertical front porch for cases where the
 *	vsync pulse width and vertical back porch time is insufficient
 *
 *	Gets # of lines to pre-fetch, then calculate VSYNC counter value.
 *	HW layer requires VSYNC counter of first pixel of tgt VFP line.
 *
 * @timing: Pointer to the intf timing information for the requested mode
 */
static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
				      const struct dpu_hw_intf_timing_params *timing)
{ … }

static void dpu_encoder_phys_vid_setup_timing_engine(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_vblank_irq(void *arg)
{ … }

static void dpu_encoder_phys_vid_underrun_irq(void *arg)
{ … }

static bool dpu_encoder_phys_vid_needs_single_flush(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_atomic_mode_set(
		struct dpu_encoder_phys *phys_enc,
		struct drm_crtc_state *crtc_state,
		struct drm_connector_state *conn_state)
{ … }

static int dpu_encoder_phys_vid_control_vblank_irq(
		struct dpu_encoder_phys *phys_enc,
		bool enable)
{ … }

static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
{ … }

static int dpu_encoder_phys_vid_wait_for_tx_complete(
		struct dpu_encoder_phys *phys_enc)
{ … }

static int dpu_encoder_phys_vid_wait_for_commit_done(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_prepare_for_kickoff(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_handle_post_kickoff(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc)
{ … }

static int dpu_encoder_phys_vid_get_line_count(
		struct dpu_encoder_phys *phys_enc)
{ … }

static int dpu_encoder_phys_vid_get_frame_count(
		struct dpu_encoder_phys *phys_enc)
{ … }

static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
{ … }

struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
		struct dpu_enc_phys_init_params *p)
{ … }