// SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/delay.h> #include <drm/drm_managed.h> #include "dpu_hwio.h" #include "dpu_hw_ctl.h" #include "dpu_kms.h" #include "dpu_trace.h" #define CTL_LAYER(lm) … #define CTL_LAYER_EXT(lm) … #define CTL_LAYER_EXT2(lm) … #define CTL_LAYER_EXT3(lm) … #define CTL_LAYER_EXT4(lm) … #define CTL_TOP … #define CTL_FLUSH … #define CTL_START … #define CTL_PREPARE … #define CTL_SW_RESET … #define CTL_LAYER_EXTN_OFFSET … #define CTL_MERGE_3D_ACTIVE … #define CTL_DSC_ACTIVE … #define CTL_WB_ACTIVE … #define CTL_INTF_ACTIVE … #define CTL_CDM_ACTIVE … #define CTL_FETCH_PIPE_ACTIVE … #define CTL_MERGE_3D_FLUSH … #define CTL_DSC_FLUSH … #define CTL_WB_FLUSH … #define CTL_INTF_FLUSH … #define CTL_CDM_FLUSH … #define CTL_PERIPH_FLUSH … #define CTL_INTF_MASTER … #define CTL_DSPP_n_FLUSH(n) … #define CTL_MIXER_BORDER_OUT … #define CTL_FLUSH_MASK_CTL … #define DPU_REG_RESET_TIMEOUT_US … #define MERGE_3D_IDX … #define DSC_IDX … #define CDM_IDX … #define PERIPH_IDX … #define INTF_IDX … #define WB_IDX … #define DSPP_IDX … #define CTL_INVALID_BIT … #define CTL_DEFAULT_GROUP_ID … static const u32 fetch_tbl[SSPP_MAX] = …; static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, enum dpu_lm lm) { … } static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) { … } static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, u32 flushbits) { … } static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { … } static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) { … } static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx, enum dpu_sspp sspp) { … } static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx, enum dpu_lm lm) { … } static void dpu_hw_ctl_update_pending_flush_intf(struct dpu_hw_ctl *ctx, enum dpu_intf intf) { … } static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx, enum dpu_wb wb) { … } static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) { … } static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx, enum dpu_wb wb) { … } static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, enum dpu_intf intf) { … } static void dpu_hw_ctl_update_pending_flush_periph_v1(struct dpu_hw_ctl *ctx, enum dpu_intf intf) { … } static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, enum dpu_merge_3d merge_3d) { … } static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx, enum dpu_dsc dsc_num) { … } static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) { … } static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) { … } static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) { … } static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) { … } static int dpu_hw_ctl_reset_control(struct dpu_hw_ctl *ctx) { … } static int dpu_hw_ctl_wait_reset_status(struct dpu_hw_ctl *ctx) { … } static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) { … } struct ctl_blend_config { … }; static const struct ctl_blend_config ctl_blend_config[][2] = …; static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg) { … } static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, struct dpu_hw_intf_cfg *cfg) { … } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, struct dpu_hw_intf_cfg *cfg) { … } static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, struct dpu_hw_intf_cfg *cfg) { … } static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, unsigned long *fetch_active) { … } static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, unsigned long cap) { if (cap & BIT(DPU_CTL_ACTIVE_CFG)) { ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1; ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1; ops->update_pending_flush_intf = dpu_hw_ctl_update_pending_flush_intf_v1; ops->update_pending_flush_periph = dpu_hw_ctl_update_pending_flush_periph_v1; ops->update_pending_flush_merge_3d = dpu_hw_ctl_update_pending_flush_merge_3d_v1; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; ops->update_pending_flush_dsc = dpu_hw_ctl_update_pending_flush_dsc_v1; ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1; } else { ops->trigger_flush = dpu_hw_ctl_trigger_flush; ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; ops->update_pending_flush_intf = dpu_hw_ctl_update_pending_flush_intf; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb; ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm; } ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush; ops->update_pending_flush = dpu_hw_ctl_update_pending_flush; ops->get_pending_flush = dpu_hw_ctl_get_pending_flush; ops->get_flush_register = dpu_hw_ctl_get_flush_register; ops->trigger_start = dpu_hw_ctl_trigger_start; ops->is_started = dpu_hw_ctl_is_started; ops->trigger_pending = dpu_hw_ctl_trigger_pending; ops->reset = dpu_hw_ctl_reset_control; ops->wait_reset_status = dpu_hw_ctl_wait_reset_status; ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages; ops->setup_blendstage = dpu_hw_ctl_setup_blendstage; ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; else ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, const struct dpu_ctl_cfg *cfg, void __iomem *addr, u32 mixer_count, const struct dpu_lm_cfg *mixer) { … }
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