linux/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
 */

#ifndef _DPU_8_0_SC8280XP_H
#define _DPU_8_0_SC8280XP_H

static const struct dpu_caps sc8280xp_dpu_caps = …;

static const struct dpu_mdp_cfg sc8280xp_mdp = …;

/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sc8280xp_ctl[] = …;

static const struct dpu_sspp_cfg sc8280xp_sspp[] = …;

static const struct dpu_lm_cfg sc8280xp_lm[] = …;

static const struct dpu_dspp_cfg sc8280xp_dspp[] = …;

static const struct dpu_pingpong_cfg sc8280xp_pp[] = …;

static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = …;

/*
 * NOTE: Each display compression engine (DCE) contains dual hard
 * slice DSC encoders so both share same base address but with
 * its own different sub block address.
 */
static const struct dpu_dsc_cfg sc8280xp_dsc[] = …;

/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
static const struct dpu_intf_cfg sc8280xp_intf[] = …;

static const struct dpu_perf_cfg sc8280xp_perf_data = …;

static const struct dpu_mdss_version sc8280xp_mdss_ver = …;

const struct dpu_mdss_cfg dpu_sc8280xp_cfg = …;

#endif