linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
 */

#include <drm/drm_managed.h>

#include "dpu_kms.h"
#include "dpu_hw_catalog.h"
#include "dpu_hwio.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_mdss.h"

#define LM_OP_MODE …
#define LM_OUT_SIZE …
#define LM_BORDER_COLOR_0 …
#define LM_BORDER_COLOR_1 …

/* These register are offset to mixer base + stage base */
#define LM_BLEND0_OP …
#define LM_BLEND0_CONST_ALPHA …
#define LM_FG_COLOR_FILL_COLOR_0 …
#define LM_FG_COLOR_FILL_COLOR_1 …
#define LM_FG_COLOR_FILL_SIZE …
#define LM_FG_COLOR_FILL_XY …

#define LM_BLEND0_FG_ALPHA …
#define LM_BLEND0_BG_ALPHA …

#define LM_MISR_CTRL …
#define LM_MISR_SIGNATURE …


/**
 * _stage_offset(): returns the relative offset of the blend registers
 * for the stage to be setup
 * @ctx:     mixer ctx contains the mixer to be programmed
 * @stage: stage index to setup
 */
static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)
{ … }

static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,
		struct dpu_hw_mixer_cfg *mixer)
{ … }

static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
		struct dpu_mdss_color *color,
		u8 border_en)
{ … }

static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
{ … }

static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
{ … }

static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
{ … }

static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
{ … }

static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
	uint32_t mixer_op_mode)
{ … }

static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops,
		unsigned long features)
{ … }

struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
				    const struct dpu_lm_cfg *cfg,
				    void __iomem *addr)
{ … }