// SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #include <linux/debugfs.h> #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_lm.h" #include "dpu_hw_sspp.h" #include "dpu_kms.h" #include "msm_mdss.h" #include <drm/drm_file.h> #include <drm/drm_managed.h> #define DPU_FETCH_CONFIG_RESET_VALUE … /* SSPP registers */ #define SSPP_SRC_SIZE … #define SSPP_SRC_XY … #define SSPP_OUT_SIZE … #define SSPP_OUT_XY … #define SSPP_SRC0_ADDR … #define SSPP_SRC1_ADDR … #define SSPP_SRC2_ADDR … #define SSPP_SRC3_ADDR … #define SSPP_SRC_YSTRIDE0 … #define SSPP_SRC_YSTRIDE1 … #define SSPP_SRC_FORMAT … #define SSPP_SRC_UNPACK_PATTERN … #define SSPP_SRC_OP_MODE … #define SSPP_SRC_CONSTANT_COLOR … #define SSPP_EXCL_REC_CTL … #define SSPP_UBWC_STATIC_CTRL … #define SSPP_FETCH_CONFIG … #define SSPP_DANGER_LUT … #define SSPP_SAFE_LUT … #define SSPP_CREQ_LUT … #define SSPP_QOS_CTRL … #define SSPP_SRC_ADDR_SW_STATUS … #define SSPP_CREQ_LUT_0 … #define SSPP_CREQ_LUT_1 … #define SSPP_DECIMATION_CONFIG … #define SSPP_SW_PIX_EXT_C0_LR … #define SSPP_SW_PIX_EXT_C0_TB … #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS … #define SSPP_SW_PIX_EXT_C1C2_LR … #define SSPP_SW_PIX_EXT_C1C2_TB … #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS … #define SSPP_SW_PIX_EXT_C3_LR … #define SSPP_SW_PIX_EXT_C3_TB … #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS … #define SSPP_TRAFFIC_SHAPER … #define SSPP_CDP_CNTL … #define SSPP_UBWC_ERROR_STATUS … #define SSPP_CDP_CNTL_REC1 … #define SSPP_TRAFFIC_SHAPER_PREFILL … #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL … #define SSPP_TRAFFIC_SHAPER_REC1 … #define SSPP_OUT_SIZE_REC1 … #define SSPP_OUT_XY_REC1 … #define SSPP_SRC_XY_REC1 … #define SSPP_SRC_SIZE_REC1 … #define SSPP_MULTIRECT_OPMODE … #define SSPP_SRC_FORMAT_REC1 … #define SSPP_SRC_UNPACK_PATTERN_REC1 … #define SSPP_SRC_OP_MODE_REC1 … #define SSPP_SRC_CONSTANT_COLOR_REC1 … #define SSPP_EXCL_REC_SIZE_REC1 … #define SSPP_EXCL_REC_XY_REC1 … #define SSPP_EXCL_REC_SIZE … #define SSPP_EXCL_REC_XY … #define SSPP_CLK_CTRL … /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ #define MDSS_MDP_OP_DEINTERLACE … #define MDSS_MDP_OP_DEINTERLACE_ODD … #define MDSS_MDP_OP_IGC_ROM_1 … #define MDSS_MDP_OP_IGC_ROM_0 … #define MDSS_MDP_OP_IGC_EN … #define MDSS_MDP_OP_FLIP_UD … #define MDSS_MDP_OP_FLIP_LR … #define MDSS_MDP_OP_BWC_EN … #define MDSS_MDP_OP_PE_OVERRIDE … #define MDSS_MDP_OP_BWC_LOSSLESS … #define MDSS_MDP_OP_BWC_Q_HIGH … #define MDSS_MDP_OP_BWC_Q_MED … /* SSPP_QOS_CTRL */ #define SSPP_QOS_CTRL_VBLANK_EN … #define SSPP_QOS_CTRL_DANGER_SAFE_EN … #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK … #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF … #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK … #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF … /* DPU_SSPP_SCALER_QSEED2 */ #define SSPP_VIG_OP_MODE … #define SCALE_CONFIG … #define COMP0_3_PHASE_STEP_X … #define COMP0_3_PHASE_STEP_Y … #define COMP1_2_PHASE_STEP_X … #define COMP1_2_PHASE_STEP_Y … #define COMP0_3_INIT_PHASE_X … #define COMP0_3_INIT_PHASE_Y … #define COMP1_2_INIT_PHASE_X … #define COMP1_2_INIT_PHASE_Y … #define VIG_0_QSEED2_SHARP … /* SSPP_TRAFFIC_SHAPER and _REC1 */ #define SSPP_TRAFFIC_SHAPER_BPC_MAX … /* * Definitions for ViG op modes */ #define VIG_OP_CSC_DST_DATAFMT … #define VIG_OP_CSC_SRC_DATAFMT … #define VIG_OP_CSC_EN … #define VIG_OP_MEM_PROT_CONT … #define VIG_OP_MEM_PROT_VAL … #define VIG_OP_MEM_PROT_SAT … #define VIG_OP_MEM_PROT_HUE … #define VIG_OP_HIST … #define VIG_OP_SKY_COL … #define VIG_OP_FOIL … #define VIG_OP_SKIN_COL … #define VIG_OP_PA_EN … #define VIG_OP_PA_SAT_ZERO_EXP … #define VIG_OP_MEM_PROT_BLEND … /* * Definitions for CSC 10 op modes */ #define SSPP_VIG_CSC_10_OP_MODE … #define VIG_CSC_10_SRC_DATAFMT … #define VIG_CSC_10_EN … #define CSC_10BIT_OFFSET … /* traffic shaper clock in Hz */ #define TS_CLK … static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { … } static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { … } static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { … } /* * Setup source pixel format, flip, */ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, const struct msm_format *fmt, u32 flags) { … } static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, struct dpu_hw_pixel_ext *pe_ext) { … } static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, const struct msm_format *format) { … } /* * dpu_hw_sspp_setup_rects() */ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg) { … } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout) { … } static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { … } static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { … } static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, struct dpu_hw_qos_cfg *cfg) { … } static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, bool danger_safe_en) { … } static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, const struct msm_format *fmt, bool enable) { … } static bool dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp *ctx, bool enable) { … } static void _setup_layer_ops(struct dpu_hw_sspp *c, unsigned long features, const struct dpu_mdss_version *mdss_rev) { … } #ifdef CONFIG_DEBUG_FS int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry) { … } #endif struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, const struct msm_mdss_data *mdss_data, const struct dpu_mdss_version *mdss_rev) { … }
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