dpu_hw_intf.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 */

#include "dpu_hwio.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_intf.h"
#include "dpu_kms.h"
#include "dpu_trace.h"

#include <linux/iopoll.h>

#include <drm/drm_managed.h>

#define INTF_TIMING_ENGINE_EN …
#define INTF_CONFIG …
#define INTF_HSYNC_CTL …
#define INTF_VSYNC_PERIOD_F0 …
#define INTF_VSYNC_PERIOD_F1 …
#define INTF_VSYNC_PULSE_WIDTH_F0 …
#define INTF_VSYNC_PULSE_WIDTH_F1 …
#define INTF_DISPLAY_V_START_F0 …
#define INTF_DISPLAY_V_START_F1 …
#define INTF_DISPLAY_V_END_F0 …
#define INTF_DISPLAY_V_END_F1 …
#define INTF_ACTIVE_V_START_F0 …
#define INTF_ACTIVE_V_START_F1 …
#define INTF_ACTIVE_V_END_F0 …
#define INTF_ACTIVE_V_END_F1 …
#define INTF_DISPLAY_HCTL …
#define INTF_ACTIVE_HCTL …
#define INTF_BORDER_COLOR …
#define INTF_UNDERFLOW_COLOR …
#define INTF_HSYNC_SKEW …
#define INTF_POLARITY_CTL …
#define INTF_TEST_CTL …
#define INTF_TP_COLOR0 …
#define INTF_TP_COLOR1 …
#define INTF_CONFIG2 …
#define INTF_DISPLAY_DATA_HCTL …
#define INTF_ACTIVE_DATA_HCTL …

#define INTF_DSI_CMD_MODE_TRIGGER_EN …
#define INTF_PANEL_FORMAT …

#define INTF_FRAME_LINE_COUNT_EN …
#define INTF_FRAME_COUNT …
#define INTF_LINE_COUNT …

#define INTF_DEFLICKER_CONFIG …
#define INTF_DEFLICKER_STRNG_COEFF …
#define INTF_DEFLICKER_WEAK_COEFF …

#define INTF_TPG_ENABLE …
#define INTF_TPG_MAIN_CONTROL …
#define INTF_TPG_VIDEO_CONFIG …
#define INTF_TPG_COMPONENT_LIMITS …
#define INTF_TPG_RECTANGLE …
#define INTF_TPG_INITIAL_VALUE …
#define INTF_TPG_BLK_WHITE_PATTERN_FRAMES …
#define INTF_TPG_RGB_MAPPING …
#define INTF_PROG_FETCH_START …
#define INTF_PROG_ROT_START …

#define INTF_MISR_CTRL …
#define INTF_MISR_SIGNATURE …

#define INTF_MUX …
#define INTF_STATUS …
#define INTF_AVR_CONTROL …
#define INTF_AVR_MODE …
#define INTF_AVR_TRIGGER …
#define INTF_AVR_VTOTAL …
#define INTF_TEAR_MDP_VSYNC_SEL …
#define INTF_TEAR_TEAR_CHECK_EN …
#define INTF_TEAR_SYNC_CONFIG_VSYNC …
#define INTF_TEAR_SYNC_CONFIG_HEIGHT …
#define INTF_TEAR_SYNC_WRCOUNT …
#define INTF_TEAR_VSYNC_INIT_VAL …
#define INTF_TEAR_INT_COUNT_VAL …
#define INTF_TEAR_SYNC_THRESH …
#define INTF_TEAR_START_POS …
#define INTF_TEAR_RD_PTR_IRQ …
#define INTF_TEAR_WR_PTR_IRQ …
#define INTF_TEAR_OUT_LINE_COUNT …
#define INTF_TEAR_LINE_COUNT …
#define INTF_TEAR_AUTOREFRESH_CONFIG …

#define INTF_CFG_ACTIVE_H_EN …
#define INTF_CFG_ACTIVE_V_EN …

#define INTF_CFG2_DATABUS_WIDEN …
#define INTF_CFG2_DATA_HCTL_EN …
#define INTF_CFG2_DCE_DATA_COMPRESS …


static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
		const struct dpu_hw_intf_timing_params *p,
		const struct msm_format *fmt,
		const struct dpu_mdss_version *mdss_ver)
{ … }

static void dpu_hw_intf_enable_timing_engine(
		struct dpu_hw_intf *intf,
		u8 enable)
{ … }

static void dpu_hw_intf_setup_prg_fetch(
		struct dpu_hw_intf *intf,
		const struct dpu_hw_intf_prog_fetch *fetch)
{ … }

static void dpu_hw_intf_bind_pingpong_blk(
		struct dpu_hw_intf *intf,
		const enum dpu_pingpong pp)
{ … }

static void dpu_hw_intf_get_status(
		struct dpu_hw_intf *intf,
		struct dpu_hw_intf_status *s)
{ … }

static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
{ … }

static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
{ … }

static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
{ … }

static int dpu_hw_intf_enable_te(struct dpu_hw_intf *intf,
		struct dpu_hw_tear_check *te)
{ … }

static void dpu_hw_intf_setup_autorefresh_config(struct dpu_hw_intf *intf,
		u32 frame_count, bool enable)
{ … }

/*
 * dpu_hw_intf_get_autorefresh_config - Get autorefresh config from HW
 * @intf:        DPU intf structure
 * @frame_count: Used to return the current frame count from hw
 *
 * Returns: True if autorefresh enabled, false if disabled.
 */
static bool dpu_hw_intf_get_autorefresh_config(struct dpu_hw_intf *intf,
		u32 *frame_count)
{ … }

static int dpu_hw_intf_disable_te(struct dpu_hw_intf *intf)
{ … }

static int dpu_hw_intf_connect_external_te(struct dpu_hw_intf *intf,
		bool enable_external_te)
{ … }

static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf,
		struct dpu_hw_pp_vsync_info *info)
{ … }

static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf,
				  enum dpu_vsync_source vsync_source)
{ … }

static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
					    uint32_t encoder_id, u16 vdisplay)
{ … }

static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf,
					     struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg)
{ … }

struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
				     const struct dpu_intf_cfg *cfg,
				     void __iomem *addr,
				     const struct dpu_mdss_version *mdss_rev)
{ … }
linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
