linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved
 */

#include <drm/drm_managed.h>

#include <drm/display/drm_dsc_helper.h>

#include "dpu_kms.h"
#include "dpu_hw_catalog.h"
#include "dpu_hwio.h"
#include "dpu_hw_mdss.h"
#include "dpu_hw_dsc.h"

#define DSC_CMN_MAIN_CNF …

/* DPU_DSC_ENC register offsets */
#define ENC_DF_CTRL …
#define ENC_GENERAL_STATUS …
#define ENC_HSLICE_STATUS …
#define ENC_OUT_STATUS …
#define ENC_INT_STAT …
#define ENC_INT_CLR …
#define ENC_INT_MASK …
#define DSC_MAIN_CONF …
#define DSC_PICTURE_SIZE …
#define DSC_SLICE_SIZE …
#define DSC_MISC_SIZE …
#define DSC_HRD_DELAYS …
#define DSC_RC_SCALE …
#define DSC_RC_SCALE_INC_DEC …
#define DSC_RC_OFFSETS_1 …
#define DSC_RC_OFFSETS_2 …
#define DSC_RC_OFFSETS_3 …
#define DSC_RC_OFFSETS_4 …
#define DSC_FLATNESS_QP …
#define DSC_RC_MODEL_SIZE …
#define DSC_RC_CONFIG …
#define DSC_RC_BUF_THRESH_0 …
#define DSC_RC_BUF_THRESH_1 …
#define DSC_RC_BUF_THRESH_2 …
#define DSC_RC_BUF_THRESH_3 …
#define DSC_RC_MIN_QP_0 …
#define DSC_RC_MIN_QP_1 …
#define DSC_RC_MIN_QP_2 …
#define DSC_RC_MAX_QP_0 …
#define DSC_RC_MAX_QP_1 …
#define DSC_RC_MAX_QP_2 …
#define DSC_RC_RANGE_BPG_OFFSETS_0 …
#define DSC_RC_RANGE_BPG_OFFSETS_1 …
#define DSC_RC_RANGE_BPG_OFFSETS_2 …

/* DPU_DSC_CTL register offsets */
#define DSC_CTL …
#define DSC_CFG …
#define DSC_DATA_IN_SWAP …
#define DSC_CLK_CTRL …

static int _dsc_calc_output_buf_max_addr(struct dpu_hw_dsc *hw_dsc, int num_softslice)
{
	int max_addr = 2400 / num_softslice;

	if (hw_dsc->caps->features & BIT(DPU_DSC_NATIVE_42x_EN))
		max_addr /= 2;

	return max_addr - 1;
};

static void dpu_hw_dsc_disable_1_2(struct dpu_hw_dsc *hw_dsc)
{ … }

static void dpu_hw_dsc_config_1_2(struct dpu_hw_dsc *hw_dsc,
				  struct drm_dsc_config *dsc,
				  u32 mode,
				  u32 initial_lines)
{ … }

static void dpu_hw_dsc_config_thresh_1_2(struct dpu_hw_dsc *hw_dsc,
					 struct drm_dsc_config *dsc)
{ … }

static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
					     const enum dpu_pingpong pp)
{ … }

static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
			       const unsigned long features)
{ … }

struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
				       const struct dpu_dsc_cfg *cfg,
				       void __iomem *addr)
{ … }