linux/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
 */

#ifndef _DPU_10_0_SM8650_H
#define _DPU_10_0_SM8650_H

static const struct dpu_caps sm8650_dpu_caps = …;

static const struct dpu_mdp_cfg sm8650_mdp = …;

/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8650_ctl[] = …;

static const struct dpu_sspp_cfg sm8650_sspp[] = …;

static const struct dpu_lm_cfg sm8650_lm[] = …;

static const struct dpu_dspp_cfg sm8650_dspp[] = …;

static const struct dpu_pingpong_cfg sm8650_pp[] = …;

static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = …;

/*
 * NOTE: Each display compression engine (DCE) contains dual hard
 * slice DSC encoders so both share same base address but with
 * its own different sub block address.
 */
static const struct dpu_dsc_cfg sm8650_dsc[] = …;

static const struct dpu_wb_cfg sm8650_wb[] = …;

static const struct dpu_intf_cfg sm8650_intf[] = …;

static const struct dpu_perf_cfg sm8650_perf_data = …;

static const struct dpu_mdss_version sm8650_mdss_ver = …;

const struct dpu_mdss_cfg dpu_sm8650_cfg = …;

#endif