linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved
  */

#include <drm/drm_managed.h>

#include "dpu_hw_mdss.h"
#include "dpu_hwio.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_wb.h"
#include "dpu_formats.h"
#include "dpu_kms.h"

#define WB_DST_FORMAT …
#define WB_DST_OP_MODE …
#define WB_DST_PACK_PATTERN …
#define WB_DST0_ADDR …
#define WB_DST1_ADDR …
#define WB_DST2_ADDR …
#define WB_DST3_ADDR …
#define WB_DST_YSTRIDE0 …
#define WB_DST_YSTRIDE1 …
#define WB_DST_YSTRIDE1 …
#define WB_DST_DITHER_BITDEPTH …
#define WB_DST_MATRIX_ROW0 …
#define WB_DST_MATRIX_ROW1 …
#define WB_DST_MATRIX_ROW2 …
#define WB_DST_MATRIX_ROW3 …
#define WB_DST_WRITE_CONFIG …
#define WB_ROTATION_DNSCALER …
#define WB_ROTATOR_PIPE_DOWNSCALER …
#define WB_N16_INIT_PHASE_X_C03 …
#define WB_N16_INIT_PHASE_X_C12 …
#define WB_N16_INIT_PHASE_Y_C03 …
#define WB_N16_INIT_PHASE_Y_C12 …
#define WB_OUT_SIZE …
#define WB_ALPHA_X_VALUE …
#define WB_DANGER_LUT …
#define WB_SAFE_LUT …
#define WB_QOS_CTRL …
#define WB_CREQ_LUT_0 …
#define WB_CREQ_LUT_1 …
#define WB_UBWC_STATIC_CTRL …
#define WB_MUX …
#define WB_CROP_CTRL …
#define WB_CROP_OFFSET …
#define WB_CLK_CTRL …
#define WB_CSC_BASE …
#define WB_DST_ADDR_SW_STATUS …
#define WB_CDP_CNTL …
#define WB_OUT_IMAGE_SIZE …
#define WB_OUT_XY …

static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx,
		struct dpu_hw_wb_cfg *data)
{ … }

static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
		struct dpu_hw_wb_cfg *data)
{ … }

static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb)
{ … }

static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
		struct dpu_hw_qos_cfg *cfg)
{ … }

static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
				const struct msm_format *fmt,
				bool enable)
{ … }

static void dpu_hw_wb_bind_pingpong_blk(
		struct dpu_hw_wb *ctx,
		const enum dpu_pingpong pp)
{ … }

static bool dpu_hw_wb_setup_clk_force_ctrl(struct dpu_hw_wb *ctx, bool enable)
{ … }

static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
		unsigned long features, const struct dpu_mdss_version *mdss_rev)
{ … }

struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev,
				 const struct dpu_wb_cfg *cfg,
				 void __iomem *addr,
				 const struct dpu_mdss_version *mdss_rev)
{ … }