// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) … #include "msm_drv.h" #include "dpu_kms.h" #include "dpu_hw_mdss.h" #include "dpu_hw_util.h" /* using a file static variables for debugfs access */ static u32 dpu_hw_util_log_mask = …; /* DPU_SCALER_QSEED3 */ #define QSEED3_HW_VERSION … #define QSEED3_OP_MODE … #define QSEED3_RGB2Y_COEFF … #define QSEED3_PHASE_INIT … #define QSEED3_PHASE_STEP_Y_H … #define QSEED3_PHASE_STEP_Y_V … #define QSEED3_PHASE_STEP_UV_H … #define QSEED3_PHASE_STEP_UV_V … #define QSEED3_PRELOAD … #define QSEED3_DE_SHARPEN … #define QSEED3_DE_SHARPEN_CTL … #define QSEED3_DE_SHAPE_CTL … #define QSEED3_DE_THRESHOLD … #define QSEED3_DE_ADJUST_DATA_0 … #define QSEED3_DE_ADJUST_DATA_1 … #define QSEED3_DE_ADJUST_DATA_2 … #define QSEED3_SRC_SIZE_Y_RGB_A … #define QSEED3_SRC_SIZE_UV … #define QSEED3_DST_SIZE … #define QSEED3_COEF_LUT_CTRL … #define QSEED3_COEF_LUT_SWAP_BIT … #define QSEED3_COEF_LUT_DIR_BIT … #define QSEED3_COEF_LUT_Y_CIR_BIT … #define QSEED3_COEF_LUT_UV_CIR_BIT … #define QSEED3_COEF_LUT_Y_SEP_BIT … #define QSEED3_COEF_LUT_UV_SEP_BIT … #define QSEED3_BUFFER_CTRL … #define QSEED3_CLK_CTRL0 … #define QSEED3_CLK_CTRL1 … #define QSEED3_CLK_STATUS … #define QSEED3_PHASE_INIT_Y_H … #define QSEED3_PHASE_INIT_Y_V … #define QSEED3_PHASE_INIT_UV_H … #define QSEED3_PHASE_INIT_UV_V … #define QSEED3_COEF_LUT … #define QSEED3_FILTERS … #define QSEED3_LUT_REGIONS … #define QSEED3_CIRCULAR_LUTS … #define QSEED3_SEPARABLE_LUTS … #define QSEED3_LUT_SIZE … #define QSEED3_ENABLE … #define QSEED3_DIR_LUT_SIZE … #define QSEED3_CIR_LUT_SIZE … #define QSEED3_SEP_LUT_SIZE … /* DPU_SCALER_QSEED3LITE */ #define QSEED3LITE_COEF_LUT_Y_SEP_BIT … #define QSEED3LITE_COEF_LUT_UV_SEP_BIT … #define QSEED3LITE_COEF_LUT_CTRL … #define QSEED3LITE_COEF_LUT_SWAP_BIT … #define QSEED3LITE_DIR_FILTER_WEIGHT … #define QSEED3LITE_FILTERS … #define QSEED3LITE_SEPARABLE_LUTS … #define QSEED3LITE_LUT_SIZE … #define QSEED3LITE_SEP_LUT_SIZE … /* QOS_LUT */ #define QOS_DANGER_LUT … #define QOS_SAFE_LUT … #define QOS_CREQ_LUT … #define QOS_QOS_CTRL … #define QOS_CREQ_LUT_0 … #define QOS_CREQ_LUT_1 … /* QOS_QOS_CTRL */ #define QOS_QOS_CTRL_DANGER_SAFE_EN … #define QOS_QOS_CTRL_DANGER_VBLANK_MASK … #define QOS_QOS_CTRL_VBLANK_EN … #define QOS_QOS_CTRL_CREQ_VBLANK_MASK … void dpu_reg_write(struct dpu_hw_blk_reg_map *c, u32 reg_off, u32 val, const char *name) { … } int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) { … } u32 *dpu_hw_util_get_log_mask_ptr(void) { … } static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset) { … } static void _dpu_hw_setup_scaler3lite_lut(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset) { … } static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset) { … } void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 scaler_offset, u32 scaler_version, const struct msm_format *format) { … } void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u32 csc_reg_off, const struct dpu_csc_cfg *data, bool csc10) { … } /** * _dpu_hw_get_qos_lut - get LUT mapping based on fill level * @tbl: Pointer to LUT table * @total_fl: fill level * Return: LUT setting corresponding to the fill level */ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, u32 total_fl) { … } void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, bool qos_8lvl, const struct dpu_hw_qos_cfg *cfg) { … } /* * note: Aside from encoders, input_sel should be set to 0x0 by default */ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u8 input_sel) { … } int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u32 misr_signature_offset, u32 *misr_value) { … } #define CDP_ENABLE … #define CDP_UBWC_META_ENABLE … #define CDP_TILE_AMORTIZE_ENABLE … #define CDP_PRELOAD_AHEAD_64 … void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, const struct msm_format *fmt, bool enable) { … } bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c, const struct dpu_clk_ctrl_reg *clk_ctrl_reg, bool enable) { … } #define TO_S15D16(_x_) … const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = …; const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = …; const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l = …;
Codebase Browser
linux