/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _DP_REG_H_ #define _DP_REG_H_ #include <linux/bitfield.h> #include <linux/bits.h> /* DP_TX Registers */ #define REG_DP_HW_VERSION … #define REG_DP_SW_RESET … #define DP_SW_RESET … #define REG_DP_PHY_CTRL … #define DP_PHY_CTRL_SW_RESET_PLL … #define DP_PHY_CTRL_SW_RESET … #define REG_DP_CLK_CTRL … #define REG_DP_CLK_ACTIVE … #define REG_DP_INTR_STATUS … #define REG_DP_INTR_STATUS2 … #define REG_DP_INTR_STATUS3 … #define REG_DP_INTR_STATUS4 … #define PSR_UPDATE_INT … #define PSR_CAPTURE_INT … #define PSR_EXIT_INT … #define PSR_UPDATE_ERROR_INT … #define PSR_WAKE_ERROR_INT … #define REG_DP_INTR_MASK4 … #define PSR_UPDATE_MASK … #define PSR_CAPTURE_MASK … #define PSR_EXIT_MASK … #define PSR_UPDATE_ERROR_MASK … #define PSR_WAKE_ERROR_MASK … #define REG_DP_DP_HPD_CTRL … #define DP_DP_HPD_CTRL_HPD_EN … #define REG_DP_DP_HPD_INT_STATUS … #define REG_DP_DP_HPD_INT_ACK … #define DP_DP_HPD_PLUG_INT_ACK … #define DP_DP_IRQ_HPD_INT_ACK … #define DP_DP_HPD_REPLUG_INT_ACK … #define DP_DP_HPD_UNPLUG_INT_ACK … #define DP_DP_HPD_STATE_STATUS_BITS_MASK … #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT … #define REG_DP_DP_HPD_INT_MASK … #define DP_DP_HPD_PLUG_INT_MASK … #define DP_DP_IRQ_HPD_INT_MASK … #define DP_DP_HPD_REPLUG_INT_MASK … #define DP_DP_HPD_UNPLUG_INT_MASK … #define DP_DP_HPD_INT_MASK … #define DP_DP_HPD_STATE_STATUS_CONNECTED … #define DP_DP_HPD_STATE_STATUS_PENDING … #define DP_DP_HPD_STATE_STATUS_DISCONNECTED … #define DP_DP_HPD_STATE_STATUS_MASK … #define REG_DP_DP_HPD_REFTIMER … #define DP_DP_HPD_REFTIMER_ENABLE … #define REG_DP_DP_HPD_EVENT_TIME_0 … #define REG_DP_DP_HPD_EVENT_TIME_1 … #define DP_DP_HPD_EVENT_TIME_0_VAL … #define DP_DP_HPD_EVENT_TIME_1_VAL … #define REG_DP_AUX_CTRL … #define DP_AUX_CTRL_ENABLE … #define DP_AUX_CTRL_RESET … #define REG_DP_AUX_DATA … #define DP_AUX_DATA_READ … #define DP_AUX_DATA_WRITE … #define DP_AUX_DATA_OFFSET … #define DP_AUX_DATA_INDEX_OFFSET … #define DP_AUX_DATA_MASK … #define DP_AUX_DATA_INDEX_WRITE … #define REG_DP_AUX_TRANS_CTRL … #define DP_AUX_TRANS_CTRL_I2C … #define DP_AUX_TRANS_CTRL_GO … #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR … #define DP_AUX_TRANS_CTRL_NO_SEND_STOP … #define REG_DP_TIMEOUT_COUNT … #define REG_DP_AUX_LIMITS … #define REG_DP_AUX_STATUS … #define DP_DPCD_CP_IRQ … #define DP_DPCD_RXSTATUS … #define DP_INTERRUPT_TRANS_NUM … #define REG_DP_MAINLINK_CTRL … #define DP_MAINLINK_CTRL_ENABLE … #define DP_MAINLINK_CTRL_RESET … #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER … #define DP_MAINLINK_CTRL_FLUSH_MODE_MASK … #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP … #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE … #define DP_MAINLINK_FB_BOUNDARY_SEL … #define REG_DP_STATE_CTRL … #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 … #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 … #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 … #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 … #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE … #define DP_STATE_CTRL_LINK_PRBS7 … #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN … #define DP_STATE_CTRL_SEND_VIDEO … #define DP_STATE_CTRL_PUSH_IDLE … #define REG_DP_CONFIGURATION_CTRL … #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK … #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN … #define DP_CONFIGURATION_CTRL_P_INTERLACED … #define DP_CONFIGURATION_CTRL_INTERLACED_BTF … #define DP_CONFIGURATION_CTRL_NUM_OF_LANES … #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING … #define DP_CONFIGURATION_CTRL_SEND_VSC … #define DP_CONFIGURATION_CTRL_BPC … #define DP_CONFIGURATION_CTRL_ASSR … #define DP_CONFIGURATION_CTRL_RGB_YUV … #define DP_CONFIGURATION_CTRL_LSCLK_DIV … #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT … #define DP_CONFIGURATION_CTRL_BPC_SHIFT … #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT … #define REG_DP_SOFTWARE_MVID … #define REG_DP_SOFTWARE_NVID … #define REG_DP_TOTAL_HOR_VER … #define REG_DP_START_HOR_VER_FROM_SYNC … #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY … #define REG_DP_ACTIVE_HOR_VER … #define REG_DP_MISC1_MISC0 … #define DP_MISC0_SYNCHRONOUS_CLK … #define DP_MISC0_COLORIMETRY_CFG_SHIFT … #define DP_MISC0_TEST_BITS_DEPTH_SHIFT … #define DP_MISC1_VSC_SDP … #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB … #define DP_MISC0_COLORIMERY_CFG_CEA_RGB … #define REG_DP_VALID_BOUNDARY … #define REG_DP_VALID_BOUNDARY_2 … #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING … #define LANE0_MAPPING_SHIFT … #define LANE1_MAPPING_SHIFT … #define LANE2_MAPPING_SHIFT … #define LANE3_MAPPING_SHIFT … #define REG_DP_MAINLINK_READY … #define DP_MAINLINK_READY_FOR_VIDEO … #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT … #define REG_DP_MAINLINK_LEVELS … #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 … #define REG_DP_TU … #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET … #define DP_HBR2_ERM_PATTERN … #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 … #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 … #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 … #define MMSS_DP_MISC1_MISC0 … #define MMSS_DP_AUDIO_TIMING_GEN … #define MMSS_DP_AUDIO_TIMING_RBR_32 … #define MMSS_DP_AUDIO_TIMING_HBR_32 … #define MMSS_DP_AUDIO_TIMING_RBR_44 … #define MMSS_DP_AUDIO_TIMING_HBR_44 … #define MMSS_DP_AUDIO_TIMING_RBR_48 … #define MMSS_DP_AUDIO_TIMING_HBR_48 … #define REG_PSR_CONFIG … #define DISABLE_PSR … #define PSR1_SUPPORTED … #define PSR2_WITHOUT_FRAMESYNC … #define PSR2_WITH_FRAMESYNC … #define REG_PSR_CMD … #define PSR_ENTER … #define PSR_EXIT … #define MMSS_DP_PSR_CRC_RG … #define MMSS_DP_PSR_CRC_B … #define REG_DP_COMPRESSION_MODE_CTRL … #define MMSS_DP_AUDIO_CFG … #define MMSS_DP_AUDIO_STATUS … #define MMSS_DP_AUDIO_PKT_CTRL … #define MMSS_DP_AUDIO_PKT_CTRL2 … #define MMSS_DP_AUDIO_ACR_CTRL … #define MMSS_DP_AUDIO_CTRL_RESET … #define MMSS_DP_SDP_CFG … #define GEN0_SDP_EN … #define MMSS_DP_SDP_CFG2 … #define MMSS_DP_AUDIO_TIMESTAMP_0 … #define MMSS_DP_AUDIO_TIMESTAMP_1 … #define GENERIC0_SDPSIZE_VALID … #define MMSS_DP_AUDIO_STREAM_0 … #define MMSS_DP_AUDIO_STREAM_1 … #define MMSS_DP_SDP_CFG3 … #define UPDATE_SDP … #define MMSS_DP_EXTENSION_0 … #define MMSS_DP_EXTENSION_1 … #define MMSS_DP_EXTENSION_2 … #define MMSS_DP_EXTENSION_3 … #define MMSS_DP_EXTENSION_4 … #define MMSS_DP_EXTENSION_5 … #define MMSS_DP_EXTENSION_6 … #define MMSS_DP_EXTENSION_7 … #define MMSS_DP_EXTENSION_8 … #define MMSS_DP_EXTENSION_9 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 … #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 … #define MMSS_DP_AUDIO_ISRC_0 … #define MMSS_DP_AUDIO_ISRC_1 … #define MMSS_DP_AUDIO_ISRC_2 … #define MMSS_DP_AUDIO_ISRC_3 … #define MMSS_DP_AUDIO_ISRC_4 … #define MMSS_DP_AUDIO_ISRC_5 … #define MMSS_DP_AUDIO_INFOFRAME_0 … #define MMSS_DP_AUDIO_INFOFRAME_1 … #define MMSS_DP_AUDIO_INFOFRAME_2 … #define MMSS_DP_GENERIC0_0 … #define MMSS_DP_GENERIC0_1 … #define MMSS_DP_GENERIC0_2 … #define MMSS_DP_GENERIC0_3 … #define MMSS_DP_GENERIC0_4 … #define MMSS_DP_GENERIC0_5 … #define MMSS_DP_GENERIC0_6 … #define MMSS_DP_GENERIC0_7 … #define MMSS_DP_GENERIC0_8 … #define MMSS_DP_GENERIC0_9 … #define MMSS_DP_GENERIC1_0 … #define MMSS_DP_GENERIC1_1 … #define MMSS_DP_GENERIC1_2 … #define MMSS_DP_GENERIC1_3 … #define MMSS_DP_GENERIC1_4 … #define MMSS_DP_GENERIC1_5 … #define MMSS_DP_GENERIC1_6 … #define MMSS_DP_GENERIC1_7 … #define MMSS_DP_GENERIC1_8 … #define MMSS_DP_GENERIC1_9 … #define MMSS_DP_VSCEXT_0 … #define MMSS_DP_VSCEXT_1 … #define MMSS_DP_VSCEXT_2 … #define MMSS_DP_VSCEXT_3 … #define MMSS_DP_VSCEXT_4 … #define MMSS_DP_VSCEXT_5 … #define MMSS_DP_VSCEXT_6 … #define MMSS_DP_VSCEXT_7 … #define MMSS_DP_VSCEXT_8 … #define MMSS_DP_VSCEXT_9 … #define MMSS_DP_BIST_ENABLE … #define DP_BIST_ENABLE_DPBIST_EN … #define MMSS_DP_TIMING_ENGINE_EN … #define DP_TIMING_ENGINE_EN_EN … #define MMSS_DP_INTF_CONFIG … #define MMSS_DP_INTF_HSYNC_CTL … #define MMSS_DP_INTF_VSYNC_PERIOD_F0 … #define MMSS_DP_INTF_VSYNC_PERIOD_F1 … #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 … #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 … #define MMSS_INTF_DISPLAY_V_START_F0 … #define MMSS_INTF_DISPLAY_V_START_F1 … #define MMSS_DP_INTF_DISPLAY_V_END_F0 … #define MMSS_DP_INTF_DISPLAY_V_END_F1 … #define MMSS_DP_INTF_ACTIVE_V_START_F0 … #define MMSS_DP_INTF_ACTIVE_V_START_F1 … #define MMSS_DP_INTF_ACTIVE_V_END_F0 … #define MMSS_DP_INTF_ACTIVE_V_END_F1 … #define MMSS_DP_INTF_DISPLAY_HCTL … #define MMSS_DP_INTF_ACTIVE_HCTL … #define MMSS_DP_INTF_POLARITY_CTL … #define MMSS_DP_TPG_MAIN_CONTROL … #define MMSS_DP_DSC_DTO … #define DP_TPG_CHECKERED_RECT_PATTERN … #define MMSS_DP_TPG_VIDEO_CONFIG … #define DP_TPG_VIDEO_CONFIG_BPP_8BIT … #define DP_TPG_VIDEO_CONFIG_RGB … #define MMSS_DP_ASYNC_FIFO_CONFIG … #define REG_DP_PHY_AUX_INTERRUPT_CLEAR … #define REG_DP_PHY_AUX_BIST_CFG … #define REG_DP_PHY_AUX_INTERRUPT_STATUS … /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL … #define DP_HDCP_STATUS … #define DP_HDCP_SW_UPPER_AKSV … #define DP_HDCP_SW_LOWER_AKSV … #define DP_HDCP_ENTROPY_CTRL0 … #define DP_HDCP_ENTROPY_CTRL1 … #define DP_HDCP_SHA_STATUS … #define DP_HDCP_RCVPORT_DATA2_0 … #define DP_HDCP_RCVPORT_DATA3 … #define DP_HDCP_RCVPORT_DATA4 … #define DP_HDCP_RCVPORT_DATA5 … #define DP_HDCP_RCVPORT_DATA6 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 … #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 … #endif /* _DP_REG_H_ */
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