linux/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>

#include "dsi_phy.h"
#include "dsi.xml.h"
#include "dsi_phy_28nm.xml.h"

/*
 * DSI PLL 28nm - clock diagram (eg: DSI0):
 *
 *         dsi0analog_postdiv_clk
 *                             |         dsi0indirect_path_div2_clk
 *                             |          |
 *                   +------+  |  +----+  |  |\   dsi0byte_mux
 *  dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \   |
 *                |  +------+     +----+     | m|  |  +----+
 *                |                          | u|--o--| /4 |-- dsi0pllbyte
 *                |                          | x|     +----+
 *                o--------------------------| /
 *                |                          |/
 *                |          +------+
 *                o----------| DIV3 |------------------------- dsi0pll
 *                           +------+
 */

#define POLL_MAX_READS …
#define POLL_TIMEOUT_US …

#define VCO_REF_CLK_RATE …
#define VCO_MIN_RATE …
#define VCO_MAX_RATE …

/* v2.0.0 28nm LP implementation */
#define DSI_PHY_28NM_QUIRK_PHY_LP …
#define DSI_PHY_28NM_QUIRK_PHY_8226 …

#define LPFR_LUT_SIZE …
struct lpfr_cfg { … };

/* Loop filter resistance: */
static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = …;

struct pll_28nm_cached_state { … };

struct dsi_pll_28nm { … };

#define to_pll_28nm(x) …

static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
				u32 nb_tries, u32 timeout_us)
{ … }

static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
{ … }

/*
 * Clock Callbacks
 */
static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
{ … }

static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{ … }

static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
{ … }

static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
{ … }

static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
{ … }

static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{ … }

static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{ … }

static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *parent_rate)
{ … }

static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = …;

static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = …;

static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = …;

/*
 * PLL Callbacks
 */

static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy)
{ … }

static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)
{ … }

static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
{ … }

static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
{ … }

static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
		struct msm_dsi_dphy_timing *timing)
{ … }

static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy)
{ … }

static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
{ … }

static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
{ … }

static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
				struct msm_dsi_phy_clk_request *clk_req)
{ … }

static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
{ … }

static const struct regulator_bulk_data dsi_phy_28nm_regulators[] = …;

const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs = …;