/* * SPDX-License-Identifier: GPL-2.0 * Copyright (c) 2018, The Linux Foundation */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/iopoll.h> #include "dsi_phy.h" #include "dsi.xml.h" #include "dsi_phy_7nm.xml.h" /* * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram * * dsi0_pll_out_div_clk dsi0_pll_bit_clk * | | * | | * +---------+ | +----------+ | +----+ * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk * +---------+ | +----------+ | +----+ * | | * | | dsi0_pll_by_2_bit_clk * | | | * | | +----+ | |\ dsi0_pclk_mux * | |--| /2 |--o--| \ | * | | +----+ | \ | +---------+ * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk * |------------------------------| / +---------+ * | +-----+ | / * -----------| /4? |--o----------|/ * +-----+ | | * | |dsiclk_sel * | * dsi0_pll_post_out_div_clk */ #define VCO_REF_CLK_RATE … #define FRAC_BITS … /* Hardware is pre V4.1 */ #define DSI_PHY_7NM_QUIRK_PRE_V4_1 … /* Hardware is V4.1 */ #define DSI_PHY_7NM_QUIRK_V4_1 … /* Hardware is V4.2 */ #define DSI_PHY_7NM_QUIRK_V4_2 … /* Hardware is V4.3 */ #define DSI_PHY_7NM_QUIRK_V4_3 … /* Hardware is V5.2 */ #define DSI_PHY_7NM_QUIRK_V5_2 … struct dsi_pll_config { … }; struct pll_7nm_cached_state { … }; struct dsi_pll_7nm { … }; #define to_pll_7nm(x) … /* * Global list of private DSI PLL struct pointers. We need this for bonded DSI * mode, where the master PLL's clk_ops needs access the slave's private data */ static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; static void dsi_pll_setup_config(struct dsi_pll_config *config) { … } static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { … } #define SSC_CENTER … #define SSC_EN … static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { … } static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { … } static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) { … } static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) { … } static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) { … } static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { … } static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { … } static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) { … } static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) { … } static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) { … } static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) { … } static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) { … } static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) { … } static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static const struct clk_ops clk_ops_dsi_pll_7nm_vco = …; /* * PLL Callbacks */ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy) { … } static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) { … } static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { … } /* * The post dividers and mux clocks are created using the standard divider and * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux * state to follow the master PLL's divider/mux state. Therefore, we don't * require special clock ops that also configure the slave PLL registers */ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) { … } static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) { … } static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) { … } static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable) { … } static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) { … } static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { … } static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) { … } static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) { … } static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = …; static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = …; static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = …; static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = …; static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = …; const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = …; const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = …;
Codebase Browser
linux