/* SPDX-License-Identifier: MIT */ /* Copyright (c) 2012-2020 NVIDIA Corporation */ #ifndef _UAPI_TEGRA_DRM_H_ #define _UAPI_TEGRA_DRM_H_ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif /* Tegra DRM legacy UAPI. Only enabled with STAGING */ #define DRM_TEGRA_GEM_CREATE_TILED … #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP … /** * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL */ struct drm_tegra_gem_create { … }; /** * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL */ struct drm_tegra_gem_mmap { … }; /** * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL */ struct drm_tegra_syncpt_read { … }; /** * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL */ struct drm_tegra_syncpt_incr { … }; /** * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL */ struct drm_tegra_syncpt_wait { … }; #define DRM_TEGRA_NO_TIMEOUT … /** * struct drm_tegra_open_channel - parameters for the open channel IOCTL */ struct drm_tegra_open_channel { … }; /** * struct drm_tegra_close_channel - parameters for the close channel IOCTL */ struct drm_tegra_close_channel { … }; /** * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL */ struct drm_tegra_get_syncpt { … }; /** * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL */ struct drm_tegra_get_syncpt_base { … }; /** * struct drm_tegra_syncpt - syncpoint increment operation */ struct drm_tegra_syncpt { … }; /** * struct drm_tegra_cmdbuf - structure describing a command buffer */ struct drm_tegra_cmdbuf { … }; /** * struct drm_tegra_reloc - GEM object relocation structure */ struct drm_tegra_reloc { … }; /** * struct drm_tegra_waitchk - wait check structure */ struct drm_tegra_waitchk { … }; /** * struct drm_tegra_submit - job submission structure */ struct drm_tegra_submit { … }; #define DRM_TEGRA_GEM_TILING_MODE_PITCH … #define DRM_TEGRA_GEM_TILING_MODE_TILED … #define DRM_TEGRA_GEM_TILING_MODE_BLOCK … /** * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL */ struct drm_tegra_gem_set_tiling { … }; /** * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL */ struct drm_tegra_gem_get_tiling { … }; #define DRM_TEGRA_GEM_BOTTOM_UP … #define DRM_TEGRA_GEM_FLAGS … /** * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL */ struct drm_tegra_gem_set_flags { … }; /** * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL */ struct drm_tegra_gem_get_flags { … }; #define DRM_TEGRA_GEM_CREATE … #define DRM_TEGRA_GEM_MMAP … #define DRM_TEGRA_SYNCPT_READ … #define DRM_TEGRA_SYNCPT_INCR … #define DRM_TEGRA_SYNCPT_WAIT … #define DRM_TEGRA_OPEN_CHANNEL … #define DRM_TEGRA_CLOSE_CHANNEL … #define DRM_TEGRA_GET_SYNCPT … #define DRM_TEGRA_SUBMIT … #define DRM_TEGRA_GET_SYNCPT_BASE … #define DRM_TEGRA_GEM_SET_TILING … #define DRM_TEGRA_GEM_GET_TILING … #define DRM_TEGRA_GEM_SET_FLAGS … #define DRM_TEGRA_GEM_GET_FLAGS … #define DRM_IOCTL_TEGRA_GEM_CREATE … #define DRM_IOCTL_TEGRA_GEM_MMAP … #define DRM_IOCTL_TEGRA_SYNCPT_READ … #define DRM_IOCTL_TEGRA_SYNCPT_INCR … #define DRM_IOCTL_TEGRA_SYNCPT_WAIT … #define DRM_IOCTL_TEGRA_OPEN_CHANNEL … #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL … #define DRM_IOCTL_TEGRA_GET_SYNCPT … #define DRM_IOCTL_TEGRA_SUBMIT … #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE … #define DRM_IOCTL_TEGRA_GEM_SET_TILING … #define DRM_IOCTL_TEGRA_GEM_GET_TILING … #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS … #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS … /* New Tegra DRM UAPI */ /* * Reported by the driver in the `capabilities` field. * * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent * with regard to the system memory. */ #define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT … struct drm_tegra_channel_open { … }; struct drm_tegra_channel_close { … }; /* * Mapping flags that can be used to influence how the mapping is created. * * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access */ #define DRM_TEGRA_CHANNEL_MAP_READ … #define DRM_TEGRA_CHANNEL_MAP_WRITE … #define DRM_TEGRA_CHANNEL_MAP_READ_WRITE … struct drm_tegra_channel_map { … }; struct drm_tegra_channel_unmap { … }; /* Submission */ /** * Specify that bit 39 of the patched-in address should be set to switch * swizzling between Tegra and non-Tegra sector layout on systems that store * surfaces in system memory in non-Tegra sector layout. */ #define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT … struct drm_tegra_submit_buf { … }; /** * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr` * buffer. Each GATHER_UPTR command uses successive words from the buffer. */ #define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR … /** * Wait for a syncpoint to reach a value before continuing with further * commands. */ #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT … /** * Wait for a syncpoint to reach a value before continuing with further * commands. The threshold is calculated relative to the start of the job. */ #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE … struct drm_tegra_submit_cmd_gather_uptr { … }; struct drm_tegra_submit_cmd_wait_syncpt { … }; struct drm_tegra_submit_cmd { … }; struct drm_tegra_submit_syncpt { … }; struct drm_tegra_channel_submit { … }; struct drm_tegra_syncpoint_allocate { … }; struct drm_tegra_syncpoint_free { … }; struct drm_tegra_syncpoint_wait { … }; #define DRM_IOCTL_TEGRA_CHANNEL_OPEN … #define DRM_IOCTL_TEGRA_CHANNEL_CLOSE … #define DRM_IOCTL_TEGRA_CHANNEL_MAP … #define DRM_IOCTL_TEGRA_CHANNEL_UNMAP … #define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT … #define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE … #define DRM_IOCTL_TEGRA_SYNCPOINT_FREE … #define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT … #if defined(__cplusplus) } #endif #endif
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