// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/delay.h> #include "dsi_phy.h" #include "dsi.xml.h" #include "dsi_phy_28nm_8960.xml.h" /* * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1): * * * +------+ * dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock) * F * byte_clk | +------+ * | bit clock divider (F / 8) * | * | +------+ * o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG * | +------+ | (sets parent rate) * | byte clock divider (F) | * | | * | o---> To esc RCG * | (doesn't set parent rate) * | * | +------+ * o-----| DIV3 |----dsi0pll------o---> To dsi RCG * +------+ | (sets parent rate) * dsi clock divider (F * magic) | * | * o---> To pixel rcg * (doesn't set parent rate) */ #define POLL_MAX_READS … #define POLL_TIMEOUT_US … #define VCO_REF_CLK_RATE … #define VCO_MIN_RATE … #define VCO_MAX_RATE … #define VCO_PREF_DIV_RATIO … struct pll_28nm_cached_state { … }; struct clk_bytediv { … }; struct dsi_pll_28nm { … }; #define to_pll_28nm(x) … static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, int nb_tries, int timeout_us) { … } /* * Clock Callbacks */ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) { … } static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) { … } static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) { … } static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static const struct clk_ops clk_ops_dsi_pll_28nm_vco = …; /* * Custom byte clock divier clk_ops * * This clock is the entry point to configuring the PLL. The user (dsi host) * will set this clock's rate to the desired byte clock rate. The VCO lock * frequency is a multiple of the byte clock rate. The multiplication factor * (shown as F in the diagram above) is a function of the byte clock rate. * * This custom divider clock ensures that its parent (VCO) is set to the * desired rate, and that the byte clock postdivider (POSTDIV2) is configured * accordingly */ #define to_clk_bytediv(_hw) … static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } /* find multiplication factor(wrt byte clock) at which the VCO should be set */ static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate) { … } static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } /* Our special byte clock divider ops */ static const struct clk_ops clk_bytediv_ops = …; /* * PLL Callbacks */ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) { … } static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) { … } static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { … } static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy) { … } static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) { … } static void dsi_28nm_phy_regulator_init(struct msm_dsi_phy *phy) { … } static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy) { … } static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy) { … } static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy) { … } static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { … } static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) { … } static const struct regulator_bulk_data dsi_phy_28nm_8960_regulators[] = …; const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = …;
Codebase Browser
linux