linux/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>

#include "dsi_phy.h"
#include "dsi.xml.h"
#include "dsi_phy_14nm.xml.h"

#define PHY_14NM_CKLN_IDX …

/*
 * DSI PLL 14nm - clock diagram (eg: DSI0):
 *
 *         dsi0n1_postdiv_clk
 *                         |
 *                         |
 *                 +----+  |  +----+
 *  dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
 *                 +----+  |  +----+
 *                         |           dsi0n1_postdivby2_clk
 *                         |   +----+  |
 *                         o---| /2 |--o--|\
 *                         |   +----+     | \   +----+
 *                         |              |  |--| n2 |-- dsi0pll
 *                         o--------------| /   +----+
 *                                        |/
 */

#define POLL_MAX_READS …
#define POLL_TIMEOUT_US …

#define VCO_REF_CLK_RATE …
#define VCO_MIN_RATE …
#define VCO_MAX_RATE …

struct dsi_pll_config { … };

struct pll_14nm_cached_state { … };

struct dsi_pll_14nm { … };

#define to_pll_14nm(x) …

/*
 * Private struct for N1/N2 post-divider clocks. These clocks are similar to
 * the generic clk_divider class of clocks. The only difference is that it
 * also sets the slave DSI PLL's post-dividers if in bonded DSI mode
 */
struct dsi_pll_14nm_postdiv { … };

#define to_pll_14nm_postdiv(_hw) …

/*
 * Global list of private DSI PLL struct pointers. We need this for bonded DSI
 * mode, where the master PLL's clk_ops needs access the slave's private data
 */
static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];

static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
				    u32 nb_tries, u32 timeout_us)
{ … }

static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
{ … }

#define CEIL(x, y) …

static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{ … }

static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{ … }

static u32 pll_14nm_kvco_slop(u32 vrate)
{ … }

static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{ … }

static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
{ … }

static void pll_db_commit_common(struct dsi_pll_14nm *pll,
				 struct dsi_pll_config *pconf)
{ … }

static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
{ … }

static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
			       struct dsi_pll_config *pconf)
{ … }

/*
 * VCO clock Callbacks
 */
static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long parent_rate)
{ … }

static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
						  unsigned long parent_rate)
{ … }

static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
{ … }

static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
{ … }

static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *parent_rate)
{ … }

static const struct clk_ops clk_ops_dsi_pll_14nm_vco = …;

/*
 * N1 and N2 post-divider clock callbacks
 */
#define div_mask(width) …
static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
						      unsigned long parent_rate)
{ … }

static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
					    unsigned long rate,
					    unsigned long *prate)
{ … }

static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
					 unsigned long parent_rate)
{ … }

static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = …;

/*
 * PLL Callbacks
 */

static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
{ … }

static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
{ … }

static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
{ … }

static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
						const char *name,
						const struct clk_hw *parent_hw,
						unsigned long flags,
						u8 shift)
{ … }

static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
{ … }

static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
{ … }

static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
				     struct msm_dsi_dphy_timing *timing,
				     int lane_idx)
{ … }

static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
			       struct msm_dsi_phy_clk_request *clk_req)
{ … }

static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
{ … }

static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = …;

static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = …;

const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = …;

const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = …;