// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Avionic Design GmbH * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ #include <linux/clk.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/iommu.h> #include <linux/interconnect.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <soc/tegra/common.h> #include <soc/tegra/pmc.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> #include <drm/drm_debugfs.h> #include <drm/drm_fourcc.h> #include <drm/drm_framebuffer.h> #include <drm/drm_vblank.h> #include "dc.h" #include "drm.h" #include "gem.h" #include "hub.h" #include "plane.h" static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state); static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) { … } /* Reads the active copy of a register. */ static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) { … } static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, unsigned int offset) { … } static inline u32 tegra_plane_readl(struct tegra_plane *plane, unsigned int offset) { … } static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, unsigned int offset) { … } bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) { … } /* * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. * Latching happens mmediately if the display controller is in STOP mode or * on the next frame boundary otherwise. * * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits * are written. When the *_ACT_REQ bits are written, the ARM copy is latched * into the ACTIVE copy, either immediately if the display controller is in * STOP mode, or at the next frame boundary otherwise. */ void tegra_dc_commit(struct tegra_dc *dc) { … } static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, unsigned int bpp) { … } static inline u32 compute_initial_dda(unsigned int in) { … } static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) { … } static void tegra_plane_setup_blending(struct tegra_plane *plane, const struct tegra_dc_window *window) { … } static bool tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, const struct tegra_dc_window *window) { … } static bool tegra_plane_use_vertical_filtering(struct tegra_plane *plane, const struct tegra_dc_window *window) { … } static void tegra_dc_setup_window(struct tegra_plane *plane, const struct tegra_dc_window *window) { … } static const u32 tegra20_primary_formats[] = …; static const u64 tegra20_modifiers[] = …; static const u32 tegra114_primary_formats[] = …; static const u32 tegra124_primary_formats[] = …; static const u64 tegra124_modifiers[] = …; static int tegra_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void tegra_plane_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void tegra_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { … } static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = …; static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) { … } static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, struct tegra_dc *dc) { … } static const u32 tegra_legacy_cursor_plane_formats[] = …; static const u32 tegra_cursor_plane_formats[] = …; static int tegra_cursor_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void __tegra_cursor_atomic_update(struct drm_plane *plane, struct drm_plane_state *new_state) { … } static void tegra_cursor_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void tegra_cursor_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) { … } static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void tegra_cursor_atomic_async_update(struct drm_plane *plane, struct drm_atomic_state *state) { … } static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = …; static const uint64_t linear_modifiers[] = …; static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, struct tegra_dc *dc) { … } static const u32 tegra20_overlay_formats[] = …; static const u32 tegra114_overlay_formats[] = …; static const u32 tegra124_overlay_formats[] = …; static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, struct tegra_dc *dc, unsigned int index, bool cursor) { … } static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, struct tegra_dc *dc) { … } static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) { … } static void tegra_dc_destroy(struct drm_crtc *crtc) { … } static void tegra_crtc_reset(struct drm_crtc *crtc) { … } static struct drm_crtc_state * tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) { … } static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) { … } #define DEBUGFS_REG32(_name) … static const struct debugfs_reg32 tegra_dc_regs[] = …; static int tegra_dc_show_regs(struct seq_file *s, void *data) { … } static int tegra_dc_show_crc(struct seq_file *s, void *data) { … } static int tegra_dc_show_stats(struct seq_file *s, void *data) { … } static struct drm_info_list debugfs_files[] = …; static int tegra_dc_late_register(struct drm_crtc *crtc) { … } static void tegra_dc_early_unregister(struct drm_crtc *crtc) { … } static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) { … } static int tegra_dc_enable_vblank(struct drm_crtc *crtc) { … } static void tegra_dc_disable_vblank(struct drm_crtc *crtc) { … } static const struct drm_crtc_funcs tegra_crtc_funcs = …; static int tegra_dc_set_timings(struct tegra_dc *dc, struct drm_display_mode *mode) { … } /** * tegra_dc_state_setup_clock - check clock settings and store them in atomic * state * @dc: display controller * @crtc_state: CRTC atomic state * @clk: parent clock for display controller * @pclk: pixel clock * @div: shift clock divider * * Returns: * 0 on success or a negative error-code on failure. */ int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct drm_crtc_state *crtc_state, struct clk *clk, unsigned long pclk, unsigned int div) { … } static void tegra_dc_update_voltage_state(struct tegra_dc *dc, struct tegra_dc_state *state) { … } static void tegra_dc_set_clock_rate(struct tegra_dc *dc, struct tegra_dc_state *state) { … } static void tegra_dc_stop(struct tegra_dc *dc) { … } static bool tegra_dc_idle(struct tegra_dc *dc) { … } static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) { … } static void tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, struct drm_atomic_state *state, bool prepare_bandwidth_transition) { … } static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static bool tegra_plane_is_cursor(const struct drm_plane_state *state) { … } static unsigned long tegra_plane_overlap_mask(struct drm_crtc_state *state, const struct drm_plane_state *plane_state) { … } static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static int tegra_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = …; static irqreturn_t tegra_dc_irq(int irq, void *data) { … } static bool tegra_dc_has_window_groups(struct tegra_dc *dc) { … } static int tegra_dc_early_init(struct host1x_client *client) { … } static int tegra_dc_init(struct host1x_client *client) { … } static int tegra_dc_exit(struct host1x_client *client) { … } static int tegra_dc_late_exit(struct host1x_client *client) { … } static int tegra_dc_runtime_suspend(struct host1x_client *client) { … } static int tegra_dc_runtime_resume(struct host1x_client *client) { … } static const struct host1x_client_ops dc_client_ops = …; static const struct tegra_dc_soc_info tegra20_dc_soc_info = …; static const struct tegra_dc_soc_info tegra30_dc_soc_info = …; static const struct tegra_dc_soc_info tegra114_dc_soc_info = …; static const struct tegra_dc_soc_info tegra124_dc_soc_info = …; static const struct tegra_dc_soc_info tegra210_dc_soc_info = …; static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = …; static const struct tegra_dc_soc_info tegra186_dc_soc_info = …; static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = …; static const struct tegra_dc_soc_info tegra194_dc_soc_info = …; static const struct of_device_id tegra_dc_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_dc_of_match); static int tegra_dc_parse_dt(struct tegra_dc *dc) { … } static int tegra_dc_match_by_pipe(struct device *dev, const void *data) { … } static int tegra_dc_couple(struct tegra_dc *dc) { … } static int tegra_dc_init_opp_table(struct tegra_dc *dc) { … } static int tegra_dc_probe(struct platform_device *pdev) { … } static void tegra_dc_remove(struct platform_device *pdev) { … } struct platform_driver tegra_dc_driver = …;
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