/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2012 Avionic Design GmbH * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ #ifndef TEGRA_HDMI_H #define TEGRA_HDMI_H … /* register definitions */ #define HDMI_CTXSW … #define HDMI_NV_PDISP_SOR_STATE0 … #define SOR_STATE_UPDATE … #define HDMI_NV_PDISP_SOR_STATE1 … #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE … #define SOR_STATE_ASY_ORMODE_NORMAL … #define SOR_STATE_ATTACHED … #define HDMI_NV_PDISP_SOR_STATE2 … #define SOR_STATE_ASY_OWNER_NONE … #define SOR_STATE_ASY_OWNER_HEAD0 … #define SOR_STATE_ASY_SUBOWNER_NONE … #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 … #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 … #define SOR_STATE_ASY_SUBOWNER_BOTH … #define SOR_STATE_ASY_CRCMODE_ACTIVE … #define SOR_STATE_ASY_CRCMODE_COMPLETE … #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE … #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A … #define SOR_STATE_ASY_PROTOCOL_CUSTOM … #define SOR_STATE_ASY_HSYNCPOL_POS … #define SOR_STATE_ASY_HSYNCPOL_NEG … #define SOR_STATE_ASY_VSYNCPOL_POS … #define SOR_STATE_ASY_VSYNCPOL_NEG … #define SOR_STATE_ASY_DEPOL_POS … #define SOR_STATE_ASY_DEPOL_NEG … #define HDMI_NV_PDISP_RG_HDCP_AN_MSB … #define HDMI_NV_PDISP_RG_HDCP_AN_LSB … #define HDMI_NV_PDISP_RG_HDCP_CN_MSB … #define HDMI_NV_PDISP_RG_HDCP_CN_LSB … #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB … #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB … #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB … #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB … #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB … #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB … #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB … #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB … #define HDMI_NV_PDISP_RG_HDCP_CTRL … #define HDMI_NV_PDISP_RG_HDCP_CMODE … #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB … #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB … #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB … #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 … #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 … #define HDMI_NV_PDISP_RG_HDCP_RI … #define HDMI_NV_PDISP_RG_HDCP_CS_MSB … #define HDMI_NV_PDISP_RG_HDCP_CS_LSB … #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 … #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 … #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 … #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 … #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL … #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS … #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER … #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW … #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW … #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH … #define INFOFRAME_CTRL_ENABLE … #define INFOFRAME_HEADER_TYPE(x) … #define INFOFRAME_HEADER_VERSION(x) … #define INFOFRAME_HEADER_LEN(x) … #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL … #define GENERIC_CTRL_ENABLE … #define GENERIC_CTRL_OTHER … #define GENERIC_CTRL_SINGLE … #define GENERIC_CTRL_HBLANK … #define GENERIC_CTRL_AUDIO … #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS … #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW … #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_CTRL … #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH … #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW … #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH … #define ACR_SUBPACK_CTS(x) … #define ACR_SUBPACK_N(x) … #define ACR_ENABLE … #define HDMI_NV_PDISP_HDMI_CTRL … #define HDMI_CTRL_REKEY(x) … #define HDMI_CTRL_MAX_AC_PACKET(x) … #define HDMI_CTRL_ENABLE … #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT … #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW … #define VSYNC_WINDOW_END(x) … #define VSYNC_WINDOW_START(x) … #define VSYNC_WINDOW_ENABLE … #define HDMI_NV_PDISP_HDMI_GCP_CTRL … #define HDMI_NV_PDISP_HDMI_GCP_STATUS … #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK … #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 … #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 … #define HDMI_NV_PDISP_HDMI_EMU0 … #define HDMI_NV_PDISP_HDMI_EMU1 … #define HDMI_NV_PDISP_HDMI_EMU1_RDATA … #define HDMI_NV_PDISP_HDMI_SPARE … #define SPARE_HW_CTS … #define SPARE_FORCE_SW_CTS … #define SPARE_CTS_RESET_VAL(x) … #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 … #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 … #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL … #define HDMI_NV_PDISP_SOR_CAP … #define HDMI_NV_PDISP_SOR_PWR … #define SOR_PWR_NORMAL_STATE_PD … #define SOR_PWR_NORMAL_STATE_PU … #define SOR_PWR_NORMAL_START_NORMAL … #define SOR_PWR_NORMAL_START_ALT … #define SOR_PWR_SAFE_STATE_PD … #define SOR_PWR_SAFE_STATE_PU … #define SOR_PWR_SETTING_NEW_DONE … #define SOR_PWR_SETTING_NEW_PENDING … #define SOR_PWR_SETTING_NEW_TRIGGER … #define HDMI_NV_PDISP_SOR_TEST … #define HDMI_NV_PDISP_SOR_PLL0 … #define SOR_PLL_PWR … #define SOR_PLL_PDBG … #define SOR_PLL_VCAPD … #define SOR_PLL_PDPORT … #define SOR_PLL_RESISTORSEL … #define SOR_PLL_PULLDOWN … #define SOR_PLL_VCOCAP(x) … #define SOR_PLL_BG_V17_S(x) … #define SOR_PLL_FILTER(x) … #define SOR_PLL_ICHPMP(x) … #define SOR_PLL_TX_REG_LOAD(x) … #define HDMI_NV_PDISP_SOR_PLL1 … #define SOR_PLL_TMDS_TERM_ENABLE … #define SOR_PLL_TMDS_TERMADJ(x) … #define SOR_PLL_LOADADJ(x) … #define SOR_PLL_PE_EN … #define SOR_PLL_HALF_FULL_PE … #define SOR_PLL_S_D_PIN_PE … #define HDMI_NV_PDISP_SOR_PLL2 … #define HDMI_NV_PDISP_SOR_CSTM … #define SOR_CSTM_ROTCLK(x) … #define SOR_CSTM_PLLDIV … #define SOR_CSTM_LVDS_ENABLE … #define SOR_CSTM_MODE_LVDS … #define SOR_CSTM_MODE_TMDS … #define SOR_CSTM_MODE_MASK … #define HDMI_NV_PDISP_SOR_LVDS … #define HDMI_NV_PDISP_SOR_CRCA … #define HDMI_NV_PDISP_SOR_CRCB … #define HDMI_NV_PDISP_SOR_BLANK … #define HDMI_NV_PDISP_SOR_SEQ_CTL … #define SOR_SEQ_PU_PC(x) … #define SOR_SEQ_PU_PC_ALT(x) … #define SOR_SEQ_PD_PC(x) … #define SOR_SEQ_PD_PC_ALT(x) … #define SOR_SEQ_PC(x) … #define SOR_SEQ_STATUS … #define SOR_SEQ_SWITCH … #define HDMI_NV_PDISP_SOR_SEQ_INST(x) … #define SOR_SEQ_INST_WAIT_TIME(x) … #define SOR_SEQ_INST_WAIT_UNITS_VSYNC … #define SOR_SEQ_INST_HALT … #define SOR_SEQ_INST_PIN_A_LOW … #define SOR_SEQ_INST_PIN_A_HIGH … #define SOR_SEQ_INST_PIN_B_LOW … #define SOR_SEQ_INST_PIN_B_HIGH … #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO … #define HDMI_NV_PDISP_SOR_VCRCA0 … #define HDMI_NV_PDISP_SOR_VCRCA1 … #define HDMI_NV_PDISP_SOR_CCRCA0 … #define HDMI_NV_PDISP_SOR_CCRCA1 … #define HDMI_NV_PDISP_SOR_EDATAA0 … #define HDMI_NV_PDISP_SOR_EDATAA1 … #define HDMI_NV_PDISP_SOR_COUNTA0 … #define HDMI_NV_PDISP_SOR_COUNTA1 … #define HDMI_NV_PDISP_SOR_DEBUGA0 … #define HDMI_NV_PDISP_SOR_DEBUGA1 … #define HDMI_NV_PDISP_SOR_TRIG … #define HDMI_NV_PDISP_SOR_MSCHECK … #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT … #define DRIVE_CURRENT_LANE0(x) … #define DRIVE_CURRENT_LANE1(x) … #define DRIVE_CURRENT_LANE2(x) … #define DRIVE_CURRENT_LANE3(x) … #define DRIVE_CURRENT_LANE0_T114(x) … #define DRIVE_CURRENT_LANE1_T114(x) … #define DRIVE_CURRENT_LANE2_T114(x) … #define DRIVE_CURRENT_LANE3_T114(x) … #define DRIVE_CURRENT_1_500_mA … #define DRIVE_CURRENT_1_875_mA … #define DRIVE_CURRENT_2_250_mA … #define DRIVE_CURRENT_2_625_mA … #define DRIVE_CURRENT_3_000_mA … #define DRIVE_CURRENT_3_375_mA … #define DRIVE_CURRENT_3_750_mA … #define DRIVE_CURRENT_4_125_mA … #define DRIVE_CURRENT_4_500_mA … #define DRIVE_CURRENT_4_875_mA … #define DRIVE_CURRENT_5_250_mA … #define DRIVE_CURRENT_5_625_mA … #define DRIVE_CURRENT_6_000_mA … #define DRIVE_CURRENT_6_375_mA … #define DRIVE_CURRENT_6_750_mA … #define DRIVE_CURRENT_7_125_mA … #define DRIVE_CURRENT_7_500_mA … #define DRIVE_CURRENT_7_875_mA … #define DRIVE_CURRENT_8_250_mA … #define DRIVE_CURRENT_8_625_mA … #define DRIVE_CURRENT_9_000_mA … #define DRIVE_CURRENT_9_375_mA … #define DRIVE_CURRENT_9_750_mA … #define DRIVE_CURRENT_10_125_mA … #define DRIVE_CURRENT_10_500_mA … #define DRIVE_CURRENT_10_875_mA … #define DRIVE_CURRENT_11_250_mA … #define DRIVE_CURRENT_11_625_mA … #define DRIVE_CURRENT_12_000_mA … #define DRIVE_CURRENT_12_375_mA … #define DRIVE_CURRENT_12_750_mA … #define DRIVE_CURRENT_13_125_mA … #define DRIVE_CURRENT_13_500_mA … #define DRIVE_CURRENT_13_875_mA … #define DRIVE_CURRENT_14_250_mA … #define DRIVE_CURRENT_14_625_mA … #define DRIVE_CURRENT_15_000_mA … #define DRIVE_CURRENT_15_375_mA … #define DRIVE_CURRENT_15_750_mA … #define DRIVE_CURRENT_16_125_mA … #define DRIVE_CURRENT_16_500_mA … #define DRIVE_CURRENT_16_875_mA … #define DRIVE_CURRENT_17_250_mA … #define DRIVE_CURRENT_17_625_mA … #define DRIVE_CURRENT_18_000_mA … #define DRIVE_CURRENT_18_375_mA … #define DRIVE_CURRENT_18_750_mA … #define DRIVE_CURRENT_19_125_mA … #define DRIVE_CURRENT_19_500_mA … #define DRIVE_CURRENT_19_875_mA … #define DRIVE_CURRENT_20_250_mA … #define DRIVE_CURRENT_20_625_mA … #define DRIVE_CURRENT_21_000_mA … #define DRIVE_CURRENT_21_375_mA … #define DRIVE_CURRENT_21_750_mA … #define DRIVE_CURRENT_22_125_mA … #define DRIVE_CURRENT_22_500_mA … #define DRIVE_CURRENT_22_875_mA … #define DRIVE_CURRENT_23_250_mA … #define DRIVE_CURRENT_23_625_mA … #define DRIVE_CURRENT_24_000_mA … #define DRIVE_CURRENT_24_375_mA … #define DRIVE_CURRENT_24_750_mA … #define DRIVE_CURRENT_0_000_mA_T114 … #define DRIVE_CURRENT_0_400_mA_T114 … #define DRIVE_CURRENT_0_800_mA_T114 … #define DRIVE_CURRENT_1_200_mA_T114 … #define DRIVE_CURRENT_1_600_mA_T114 … #define DRIVE_CURRENT_2_000_mA_T114 … #define DRIVE_CURRENT_2_400_mA_T114 … #define DRIVE_CURRENT_2_800_mA_T114 … #define DRIVE_CURRENT_3_200_mA_T114 … #define DRIVE_CURRENT_3_600_mA_T114 … #define DRIVE_CURRENT_4_000_mA_T114 … #define DRIVE_CURRENT_4_400_mA_T114 … #define DRIVE_CURRENT_4_800_mA_T114 … #define DRIVE_CURRENT_5_200_mA_T114 … #define DRIVE_CURRENT_5_600_mA_T114 … #define DRIVE_CURRENT_6_000_mA_T114 … #define DRIVE_CURRENT_6_400_mA_T114 … #define DRIVE_CURRENT_6_800_mA_T114 … #define DRIVE_CURRENT_7_200_mA_T114 … #define DRIVE_CURRENT_7_600_mA_T114 … #define DRIVE_CURRENT_8_000_mA_T114 … #define DRIVE_CURRENT_8_400_mA_T114 … #define DRIVE_CURRENT_8_800_mA_T114 … #define DRIVE_CURRENT_9_200_mA_T114 … #define DRIVE_CURRENT_9_600_mA_T114 … #define DRIVE_CURRENT_10_000_mA_T114 … #define DRIVE_CURRENT_10_400_mA_T114 … #define DRIVE_CURRENT_10_800_mA_T114 … #define DRIVE_CURRENT_11_200_mA_T114 … #define DRIVE_CURRENT_11_600_mA_T114 … #define DRIVE_CURRENT_12_000_mA_T114 … #define DRIVE_CURRENT_12_400_mA_T114 … #define DRIVE_CURRENT_12_800_mA_T114 … #define DRIVE_CURRENT_13_200_mA_T114 … #define DRIVE_CURRENT_13_600_mA_T114 … #define DRIVE_CURRENT_14_000_mA_T114 … #define DRIVE_CURRENT_14_400_mA_T114 … #define DRIVE_CURRENT_14_800_mA_T114 … #define DRIVE_CURRENT_15_200_mA_T114 … #define DRIVE_CURRENT_15_600_mA_T114 … #define DRIVE_CURRENT_16_000_mA_T114 … #define DRIVE_CURRENT_16_400_mA_T114 … #define DRIVE_CURRENT_16_800_mA_T114 … #define DRIVE_CURRENT_17_200_mA_T114 … #define DRIVE_CURRENT_17_600_mA_T114 … #define DRIVE_CURRENT_18_000_mA_T114 … #define DRIVE_CURRENT_18_400_mA_T114 … #define DRIVE_CURRENT_18_800_mA_T114 … #define DRIVE_CURRENT_19_200_mA_T114 … #define DRIVE_CURRENT_19_600_mA_T114 … #define DRIVE_CURRENT_20_000_mA_T114 … #define DRIVE_CURRENT_20_400_mA_T114 … #define DRIVE_CURRENT_20_800_mA_T114 … #define DRIVE_CURRENT_21_200_mA_T114 … #define DRIVE_CURRENT_21_600_mA_T114 … #define DRIVE_CURRENT_22_000_mA_T114 … #define DRIVE_CURRENT_22_400_mA_T114 … #define DRIVE_CURRENT_22_800_mA_T114 … #define DRIVE_CURRENT_23_200_mA_T114 … #define DRIVE_CURRENT_23_600_mA_T114 … #define DRIVE_CURRENT_24_000_mA_T114 … #define DRIVE_CURRENT_24_400_mA_T114 … #define DRIVE_CURRENT_24_800_mA_T114 … #define DRIVE_CURRENT_25_200_mA_T114 … #define DRIVE_CURRENT_25_400_mA_T114 … #define DRIVE_CURRENT_25_800_mA_T114 … #define DRIVE_CURRENT_26_200_mA_T114 … #define DRIVE_CURRENT_26_600_mA_T114 … #define DRIVE_CURRENT_27_000_mA_T114 … #define DRIVE_CURRENT_27_400_mA_T114 … #define DRIVE_CURRENT_27_800_mA_T114 … #define DRIVE_CURRENT_28_200_mA_T114 … #define HDMI_NV_PDISP_AUDIO_DEBUG0 … #define HDMI_NV_PDISP_AUDIO_DEBUG1 … #define HDMI_NV_PDISP_AUDIO_DEBUG2 … #define HDMI_NV_PDISP_AUDIO_FS(x) … #define AUDIO_FS_LOW(x) … #define AUDIO_FS_HIGH(x) … #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH … #define HDMI_NV_PDISP_AUDIO_THRESHOLD … #define HDMI_NV_PDISP_AUDIO_CNTRL0 … #define AUDIO_CNTRL0_ERROR_TOLERANCE(x) … #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO … #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF … #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL … #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) … #define HDMI_NV_PDISP_AUDIO_N … #define AUDIO_N_VALUE(x) … #define AUDIO_N_RESETF … #define AUDIO_N_GENERATE_NORMAL … #define AUDIO_N_GENERATE_ALTERNATE … #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING … #define HDMI_NV_PDISP_SOR_REFCLK … #define SOR_REFCLK_DIV_INT(x) … #define SOR_REFCLK_DIV_FRAC(x) … #define HDMI_NV_PDISP_CRC_CONTROL … #define HDMI_NV_PDISP_INPUT_CONTROL … #define HDMI_SRC_DISPLAYA … #define HDMI_SRC_DISPLAYB … #define ARM_VIDEO_RANGE_FULL … #define ARM_VIDEO_RANGE_LIMITED … #define HDMI_NV_PDISP_SCRATCH … #define HDMI_NV_PDISP_PE_CURRENT … #define PE_CURRENT0(x) … #define PE_CURRENT1(x) … #define PE_CURRENT2(x) … #define PE_CURRENT3(x) … #define PE_CURRENT_0_0_mA … #define PE_CURRENT_0_5_mA … #define PE_CURRENT_1_0_mA … #define PE_CURRENT_1_5_mA … #define PE_CURRENT_2_0_mA … #define PE_CURRENT_2_5_mA … #define PE_CURRENT_3_0_mA … #define PE_CURRENT_3_5_mA … #define PE_CURRENT_4_0_mA … #define PE_CURRENT_4_5_mA … #define PE_CURRENT_5_0_mA … #define PE_CURRENT_5_5_mA … #define PE_CURRENT_6_0_mA … #define PE_CURRENT_6_5_mA … #define PE_CURRENT_7_0_mA … #define PE_CURRENT_7_5_mA … #define PE_CURRENT_0_mA_T114 … #define PE_CURRENT_1_mA_T114 … #define PE_CURRENT_2_mA_T114 … #define PE_CURRENT_3_mA_T114 … #define PE_CURRENT_4_mA_T114 … #define PE_CURRENT_5_mA_T114 … #define PE_CURRENT_6_mA_T114 … #define PE_CURRENT_7_mA_T114 … #define PE_CURRENT_8_mA_T114 … #define PE_CURRENT_9_mA_T114 … #define PE_CURRENT_10_mA_T114 … #define PE_CURRENT_11_mA_T114 … #define PE_CURRENT_12_mA_T114 … #define PE_CURRENT_13_mA_T114 … #define PE_CURRENT_14_mA_T114 … #define PE_CURRENT_15_mA_T114 … #define HDMI_NV_PDISP_KEY_CTRL … #define HDMI_NV_PDISP_KEY_DEBUG0 … #define HDMI_NV_PDISP_KEY_DEBUG1 … #define HDMI_NV_PDISP_KEY_DEBUG2 … #define HDMI_NV_PDISP_KEY_HDCP_KEY_0 … #define HDMI_NV_PDISP_KEY_HDCP_KEY_1 … #define HDMI_NV_PDISP_KEY_HDCP_KEY_2 … #define HDMI_NV_PDISP_KEY_HDCP_KEY_3 … #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG … #define HDMI_NV_PDISP_KEY_SKEY_INDEX … #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 … #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO … #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF … #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL … #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL … #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 … #define SOR_AUDIO_SPARE0_HBR_ENABLE … #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 … #define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID … #define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK … #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 … #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR … #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE … #define SOR_AUDIO_HDA_PRESENSE_VALID … #define SOR_AUDIO_HDA_PRESENSE_PRESENT … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 … #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT … #define HDMI_NV_PDISP_INT_STATUS … #define INT_SCRATCH … #define INT_CP_REQUEST … #define INT_CODEC_SCRATCH1 … #define INT_CODEC_SCRATCH0 … #define HDMI_NV_PDISP_INT_MASK … #define HDMI_NV_PDISP_INT_ENABLE … #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT … #define PEAK_CURRENT_LANE0(x) … #define PEAK_CURRENT_LANE1(x) … #define PEAK_CURRENT_LANE2(x) … #define PEAK_CURRENT_LANE3(x) … #define PEAK_CURRENT_0_000_mA … #define PEAK_CURRENT_0_200_mA … #define PEAK_CURRENT_0_400_mA … #define PEAK_CURRENT_0_600_mA … #define PEAK_CURRENT_0_800_mA … #define PEAK_CURRENT_1_000_mA … #define PEAK_CURRENT_1_200_mA … #define PEAK_CURRENT_1_400_mA … #define PEAK_CURRENT_1_600_mA … #define PEAK_CURRENT_1_800_mA … #define PEAK_CURRENT_2_000_mA … #define PEAK_CURRENT_2_200_mA … #define PEAK_CURRENT_2_400_mA … #define PEAK_CURRENT_2_600_mA … #define PEAK_CURRENT_2_800_mA … #define PEAK_CURRENT_3_000_mA … #define PEAK_CURRENT_3_200_mA … #define PEAK_CURRENT_3_400_mA … #define PEAK_CURRENT_3_600_mA … #define PEAK_CURRENT_3_800_mA … #define PEAK_CURRENT_4_000_mA … #define PEAK_CURRENT_4_200_mA … #define PEAK_CURRENT_4_400_mA … #define PEAK_CURRENT_4_600_mA … #define PEAK_CURRENT_4_800_mA … #define PEAK_CURRENT_5_000_mA … #define PEAK_CURRENT_5_200_mA … #define PEAK_CURRENT_5_400_mA … #define PEAK_CURRENT_5_600_mA … #define PEAK_CURRENT_5_800_mA … #define PEAK_CURRENT_6_000_mA … #define PEAK_CURRENT_6_200_mA … #define PEAK_CURRENT_6_400_mA … #define PEAK_CURRENT_6_600_mA … #define PEAK_CURRENT_6_800_mA … #define PEAK_CURRENT_7_000_mA … #define PEAK_CURRENT_7_200_mA … #define PEAK_CURRENT_7_400_mA … #define PEAK_CURRENT_7_600_mA … #define PEAK_CURRENT_7_800_mA … #define PEAK_CURRENT_8_000_mA … #define PEAK_CURRENT_8_200_mA … #define PEAK_CURRENT_8_400_mA … #define PEAK_CURRENT_8_600_mA … #define PEAK_CURRENT_8_800_mA … #define PEAK_CURRENT_9_000_mA … #define PEAK_CURRENT_9_200_mA … #define PEAK_CURRENT_9_400_mA … #define HDMI_NV_PDISP_SOR_PAD_CTLS0 … #endif /* TEGRA_HDMI_H */
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