linux/drivers/gpu/drm/tegra/sor.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2013 NVIDIA Corporation
 */

#ifndef DRM_TEGRA_SOR_H
#define DRM_TEGRA_SOR_H

#define SOR_CTXSW

#define SOR_SUPER_STATE0

#define SOR_SUPER_STATE1
#define SOR_SUPER_STATE_ATTACHED
#define SOR_SUPER_STATE_MODE_NORMAL
#define SOR_SUPER_STATE_HEAD_MODE_MASK
#define SOR_SUPER_STATE_HEAD_MODE_AWAKE
#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE
#define SOR_SUPER_STATE_HEAD_MODE_SLEEP

#define SOR_STATE0

#define SOR_STATE1
#define SOR_STATE_ASY_PIXELDEPTH_MASK
#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
#define SOR_STATE_ASY_PIXELDEPTH_BPP_30_444
#define SOR_STATE_ASY_PIXELDEPTH_BPP_36_444
#define SOR_STATE_ASY_PIXELDEPTH_BPP_48_444
#define SOR_STATE_ASY_VSYNCPOL
#define SOR_STATE_ASY_HSYNCPOL
#define SOR_STATE_ASY_PROTOCOL_MASK
#define SOR_STATE_ASY_PROTOCOL_CUSTOM
#define SOR_STATE_ASY_PROTOCOL_DP_A
#define SOR_STATE_ASY_PROTOCOL_DP_B
#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A
#define SOR_STATE_ASY_PROTOCOL_LVDS
#define SOR_STATE_ASY_CRC_MODE_MASK
#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE
#define SOR_STATE_ASY_CRC_MODE_COMPLETE
#define SOR_STATE_ASY_CRC_MODE_ACTIVE
#define SOR_STATE_ASY_SUBOWNER_MASK
#define SOR_STATE_ASY_OWNER_MASK
#define SOR_STATE_ASY_OWNER(x)

#define SOR_HEAD_STATE0(x)
#define SOR_HEAD_STATE_RANGECOMPRESS_MASK
#define SOR_HEAD_STATE_DYNRANGE_MASK
#define SOR_HEAD_STATE_DYNRANGE_VESA
#define SOR_HEAD_STATE_DYNRANGE_CEA
#define SOR_HEAD_STATE_COLORSPACE_MASK
#define SOR_HEAD_STATE_COLORSPACE_RGB
#define SOR_HEAD_STATE1(x)
#define SOR_HEAD_STATE2(x)
#define SOR_HEAD_STATE3(x)
#define SOR_HEAD_STATE4(x)
#define SOR_HEAD_STATE5(x)
#define SOR_CRC_CNTRL
#define SOR_CRC_CNTRL_ENABLE
#define SOR_DP_DEBUG_MVID

#define SOR_CLK_CNTRL
#define SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
#define SOR_CLK_CNTRL_DP_LINK_SPEED(x)
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40
#define SOR_CLK_CNTRL_DP_CLK_SEL_MASK
#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK
#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK
#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK
#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK

#define SOR_CAP

#define SOR_PWR
#define SOR_PWR_TRIGGER
#define SOR_PWR_MODE_SAFE
#define SOR_PWR_NORMAL_STATE_PU

#define SOR_TEST
#define SOR_TEST_CRC_POST_SERIALIZE
#define SOR_TEST_ATTACHED
#define SOR_TEST_HEAD_MODE_MASK
#define SOR_TEST_HEAD_MODE_AWAKE

#define SOR_PLL0
#define SOR_PLL0_ICHPMP_MASK
#define SOR_PLL0_ICHPMP(x)
#define SOR_PLL0_FILTER_MASK
#define SOR_PLL0_FILTER(x)
#define SOR_PLL0_VCOCAP_MASK
#define SOR_PLL0_VCOCAP(x)
#define SOR_PLL0_VCOCAP_RST
#define SOR_PLL0_PLLREG_MASK
#define SOR_PLL0_PLLREG_LEVEL(x)
#define SOR_PLL0_PLLREG_LEVEL_V25
#define SOR_PLL0_PLLREG_LEVEL_V15
#define SOR_PLL0_PLLREG_LEVEL_V35
#define SOR_PLL0_PLLREG_LEVEL_V45
#define SOR_PLL0_PULLDOWN
#define SOR_PLL0_RESISTOR_EXT
#define SOR_PLL0_VCOPD
#define SOR_PLL0_PWR

#define SOR_PLL1
/* XXX: read-only bit? */
#define SOR_PLL1_LOADADJ_MASK
#define SOR_PLL1_LOADADJ(x)
#define SOR_PLL1_TERM_COMPOUT
#define SOR_PLL1_TMDS_TERMADJ_MASK
#define SOR_PLL1_TMDS_TERMADJ(x)
#define SOR_PLL1_TMDS_TERM

#define SOR_PLL2
#define SOR_PLL2_LVDS_ENABLE
#define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
#define SOR_PLL2_PORT_POWERDOWN
#define SOR_PLL2_BANDGAP_POWERDOWN
#define SOR_PLL2_POWERDOWN_OVERRIDE
#define SOR_PLL2_SEQ_PLLCAPPD
#define SOR_PLL2_SEQ_PLL_PULLDOWN

#define SOR_PLL3
#define SOR_PLL3_BG_TEMP_COEF_MASK
#define SOR_PLL3_BG_TEMP_COEF(x)
#define SOR_PLL3_BG_VREF_LEVEL_MASK
#define SOR_PLL3_BG_VREF_LEVEL(x)
#define SOR_PLL3_PLL_VDD_MODE_1V8
#define SOR_PLL3_PLL_VDD_MODE_3V3
#define SOR_PLL3_AVDD10_LEVEL_MASK
#define SOR_PLL3_AVDD10_LEVEL(x)
#define SOR_PLL3_AVDD14_LEVEL_MASK
#define SOR_PLL3_AVDD14_LEVEL(x)

#define SOR_CSTM
#define SOR_CSTM_ROTCLK_MASK
#define SOR_CSTM_ROTCLK(x)
#define SOR_CSTM_LVDS
#define SOR_CSTM_LINK_ACT_B
#define SOR_CSTM_LINK_ACT_A
#define SOR_CSTM_UPPER

#define SOR_LVDS
#define SOR_CRCA
#define SOR_CRCA_VALID
#define SOR_CRCA_RESET
#define SOR_CRCB
#define SOR_BLANK
#define SOR_SEQ_CTL
#define SOR_SEQ_CTL_PD_PC_ALT(x)
#define SOR_SEQ_CTL_PD_PC(x)
#define SOR_SEQ_CTL_PU_PC_ALT(x)
#define SOR_SEQ_CTL_PU_PC(x)

#define SOR_LANE_SEQ_CTL
#define SOR_LANE_SEQ_CTL_TRIGGER
#define SOR_LANE_SEQ_CTL_STATE_BUSY
#define SOR_LANE_SEQ_CTL_SEQUENCE_UP
#define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
#define SOR_LANE_SEQ_CTL_POWER_STATE_UP
#define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN
#define SOR_LANE_SEQ_CTL_DELAY(x)

#define SOR_SEQ_INST(x)
#define SOR_SEQ_INST_PLL_PULLDOWN
#define SOR_SEQ_INST_POWERDOWN_MACRO
#define SOR_SEQ_INST_ASSERT_PLL_RESET
#define SOR_SEQ_INST_BLANK_V
#define SOR_SEQ_INST_BLANK_H
#define SOR_SEQ_INST_BLANK_DE
#define SOR_SEQ_INST_BLACK_DATA
#define SOR_SEQ_INST_TRISTATE_IOS
#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO
#define SOR_SEQ_INST_PIN_B_LOW
#define SOR_SEQ_INST_PIN_B_HIGH
#define SOR_SEQ_INST_PIN_A_LOW
#define SOR_SEQ_INST_PIN_A_HIGH
#define SOR_SEQ_INST_SEQUENCE_UP
#define SOR_SEQ_INST_SEQUENCE_DOWN
#define SOR_SEQ_INST_LANE_SEQ_STOP
#define SOR_SEQ_INST_LANE_SEQ_RUN
#define SOR_SEQ_INST_PORT_POWERDOWN
#define SOR_SEQ_INST_PLL_POWERDOWN
#define SOR_SEQ_INST_HALT
#define SOR_SEQ_INST_WAIT_US
#define SOR_SEQ_INST_WAIT_MS
#define SOR_SEQ_INST_WAIT_VSYNC
#define SOR_SEQ_INST_WAIT(x)

#define SOR_PWM_DIV
#define SOR_PWM_DIV_MASK

#define SOR_PWM_CTL
#define SOR_PWM_CTL_TRIGGER
#define SOR_PWM_CTL_CLK_SEL
#define SOR_PWM_CTL_DUTY_CYCLE_MASK

#define SOR_VCRC_A0
#define SOR_VCRC_A1
#define SOR_VCRC_B0
#define SOR_VCRC_B1
#define SOR_CCRC_A0
#define SOR_CCRC_A1
#define SOR_CCRC_B0
#define SOR_CCRC_B1
#define SOR_EDATA_A0
#define SOR_EDATA_A1
#define SOR_EDATA_B0
#define SOR_EDATA_B1
#define SOR_COUNT_A0
#define SOR_COUNT_A1
#define SOR_COUNT_B0
#define SOR_COUNT_B1
#define SOR_DEBUG_A0
#define SOR_DEBUG_A1
#define SOR_DEBUG_B0
#define SOR_DEBUG_B1
#define SOR_TRIG
#define SOR_MSCHECK
#define SOR_XBAR_CTRL
#define SOR_XBAR_CTRL_LINK1_XSEL(channel, value)
#define SOR_XBAR_CTRL_LINK0_XSEL(channel, value)
#define SOR_XBAR_CTRL_LINK_SWAP
#define SOR_XBAR_CTRL_BYPASS
#define SOR_XBAR_POL

#define SOR_DP_LINKCTL0
#define SOR_DP_LINKCTL_LANE_COUNT_MASK
#define SOR_DP_LINKCTL_LANE_COUNT(x)
#define SOR_DP_LINKCTL_ENHANCED_FRAME
#define SOR_DP_LINKCTL_TU_SIZE_MASK
#define SOR_DP_LINKCTL_TU_SIZE(x)
#define SOR_DP_LINKCTL_ENABLE

#define SOR_DP_LINKCTL1

#define SOR_LANE_DRIVE_CURRENT0
#define SOR_LANE_DRIVE_CURRENT1
#define SOR_LANE4_DRIVE_CURRENT0
#define SOR_LANE4_DRIVE_CURRENT1
#define SOR_LANE_DRIVE_CURRENT_LANE3(x)
#define SOR_LANE_DRIVE_CURRENT_LANE2(x)
#define SOR_LANE_DRIVE_CURRENT_LANE1(x)
#define SOR_LANE_DRIVE_CURRENT_LANE0(x)

#define SOR_LANE_PREEMPHASIS0
#define SOR_LANE_PREEMPHASIS1
#define SOR_LANE4_PREEMPHASIS0
#define SOR_LANE4_PREEMPHASIS1
#define SOR_LANE_PREEMPHASIS_LANE3(x)
#define SOR_LANE_PREEMPHASIS_LANE2(x)
#define SOR_LANE_PREEMPHASIS_LANE1(x)
#define SOR_LANE_PREEMPHASIS_LANE0(x)

#define SOR_LANE_POSTCURSOR0
#define SOR_LANE_POSTCURSOR1
#define SOR_LANE_POSTCURSOR_LANE3(x)
#define SOR_LANE_POSTCURSOR_LANE2(x)
#define SOR_LANE_POSTCURSOR_LANE1(x)
#define SOR_LANE_POSTCURSOR_LANE0(x)

#define SOR_DP_CONFIG0
#define SOR_DP_CONFIG_DISPARITY_NEGATIVE
#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE
#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY
#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK
#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x)
#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK
#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x)
#define SOR_DP_CONFIG_WATERMARK_MASK
#define SOR_DP_CONFIG_WATERMARK(x)

#define SOR_DP_CONFIG1
#define SOR_DP_MN0
#define SOR_DP_MN1

#define SOR_DP_PADCTL0
#define SOR_DP_PADCTL_PAD_CAL_PD
#define SOR_DP_PADCTL_TX_PU_ENABLE
#define SOR_DP_PADCTL_TX_PU_MASK
#define SOR_DP_PADCTL_TX_PU(x)
#define SOR_DP_PADCTL_CM_TXD_3
#define SOR_DP_PADCTL_CM_TXD_2
#define SOR_DP_PADCTL_CM_TXD_1
#define SOR_DP_PADCTL_CM_TXD_0
#define SOR_DP_PADCTL_CM_TXD(x)
#define SOR_DP_PADCTL_PD_TXD_3
#define SOR_DP_PADCTL_PD_TXD_0
#define SOR_DP_PADCTL_PD_TXD_1
#define SOR_DP_PADCTL_PD_TXD_2
#define SOR_DP_PADCTL_PD_TXD(x)

#define SOR_DP_PADCTL1

#define SOR_DP_DEBUG0
#define SOR_DP_DEBUG1

#define SOR_DP_SPARE0
#define SOR_DP_SPARE_DISP_VIDEO_PREAMBLE
#define SOR_DP_SPARE_MACRO_SOR_CLK
#define SOR_DP_SPARE_PANEL_INTERNAL
#define SOR_DP_SPARE_SEQ_ENABLE

#define SOR_DP_SPARE1
#define SOR_DP_AUDIO_CTRL

#define SOR_DP_AUDIO_HBLANK_SYMBOLS
#define SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK

#define SOR_DP_AUDIO_VBLANK_SYMBOLS
#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK

#define SOR_DP_GENERIC_INFOFRAME_HEADER
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK0
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK1
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK2
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK3
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK4
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK5
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK6

#define SOR_DP_TPG
#define SOR_DP_TPG_CHANNEL_CODING
#define SOR_DP_TPG_SCRAMBLER_MASK
#define SOR_DP_TPG_SCRAMBLER_FIBONACCI
#define SOR_DP_TPG_SCRAMBLER_GALIOS
#define SOR_DP_TPG_SCRAMBLER_NONE
#define SOR_DP_TPG_PATTERN_MASK
#define SOR_DP_TPG_PATTERN_HBR2
#define SOR_DP_TPG_PATTERN_CSTM
#define SOR_DP_TPG_PATTERN_PRBS7
#define SOR_DP_TPG_PATTERN_SBLERRRATE
#define SOR_DP_TPG_PATTERN_D102
#define SOR_DP_TPG_PATTERN_TRAIN3
#define SOR_DP_TPG_PATTERN_TRAIN2
#define SOR_DP_TPG_PATTERN_TRAIN1
#define SOR_DP_TPG_PATTERN_NONE

#define SOR_DP_TPG_CONFIG
#define SOR_DP_LQ_CSTM0
#define SOR_DP_LQ_CSTM1
#define SOR_DP_LQ_CSTM2

#define SOR_DP_PADCTL2
#define SOR_DP_PADCTL_SPAREPLL_MASK
#define SOR_DP_PADCTL_SPAREPLL(x)

#define SOR_HDMI_AUDIO_INFOFRAME_CTRL
#define SOR_HDMI_AUDIO_INFOFRAME_STATUS
#define SOR_HDMI_AUDIO_INFOFRAME_HEADER

#define SOR_HDMI_AVI_INFOFRAME_CTRL
#define INFOFRAME_CTRL_CHECKSUM_ENABLE
#define INFOFRAME_CTRL_SINGLE
#define INFOFRAME_CTRL_OTHER
#define INFOFRAME_CTRL_ENABLE

#define SOR_HDMI_AVI_INFOFRAME_STATUS
#define INFOFRAME_STATUS_DONE

#define SOR_HDMI_AVI_INFOFRAME_HEADER
#define INFOFRAME_HEADER_LEN(x)
#define INFOFRAME_HEADER_VERSION(x)
#define INFOFRAME_HEADER_TYPE(x)

#define SOR_HDMI_ACR_CTRL

#define SOR_HDMI_ACR_0320_SUBPACK_LOW
#define SOR_HDMI_ACR_SUBPACK_LOW_SB1(x)

#define SOR_HDMI_ACR_0320_SUBPACK_HIGH
#define SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE

#define SOR_HDMI_ACR_0441_SUBPACK_LOW
#define SOR_HDMI_ACR_0441_SUBPACK_HIGH

#define SOR_HDMI_CTRL
#define SOR_HDMI_CTRL_ENABLE
#define SOR_HDMI_CTRL_MAX_AC_PACKET(x)
#define SOR_HDMI_CTRL_AUDIO_LAYOUT
#define SOR_HDMI_CTRL_REKEY(x)

#define SOR_HDMI_SPARE
#define SOR_HDMI_SPARE_ACR_PRIORITY_HIGH
#define SOR_HDMI_SPARE_CTS_RESET(x)
#define SOR_HDMI_SPARE_HW_CTS_ENABLE

#define SOR_REFCLK
#define SOR_REFCLK_DIV_INT(x)
#define SOR_REFCLK_DIV_FRAC(x)

#define SOR_INPUT_CONTROL
#define SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED
#define SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x)

#define SOR_AUDIO_CNTRL
#define SOR_AUDIO_CNTRL_INJECT_NULLSMPL
#define SOR_AUDIO_CNTRL_SOURCE_SELECT(x)
#define SOURCE_SELECT_MASK
#define SOURCE_SELECT_HDA
#define SOURCE_SELECT_SPDIF
#define SOURCE_SELECT_AUTO
#define SOR_AUDIO_CNTRL_AFIFO_FLUSH

#define SOR_AUDIO_SPARE
#define SOR_AUDIO_SPARE_HBR_ENABLE

#define SOR_AUDIO_NVAL_0320
#define SOR_AUDIO_NVAL_0441
#define SOR_AUDIO_NVAL_0882
#define SOR_AUDIO_NVAL_1764
#define SOR_AUDIO_NVAL_0480
#define SOR_AUDIO_NVAL_0960
#define SOR_AUDIO_NVAL_1920

#define SOR_AUDIO_HDA_CODEC_SCRATCH0
#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID
#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK

#define SOR_AUDIO_HDA_ELD_BUFWR
#define SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x)
#define SOR_AUDIO_HDA_ELD_BUFWR_DATA(x)

#define SOR_AUDIO_HDA_PRESENSE
#define SOR_AUDIO_HDA_PRESENSE_ELDV
#define SOR_AUDIO_HDA_PRESENSE_PD

#define SOR_AUDIO_AVAL_0320
#define SOR_AUDIO_AVAL_0441
#define SOR_AUDIO_AVAL_0882
#define SOR_AUDIO_AVAL_1764
#define SOR_AUDIO_AVAL_0480
#define SOR_AUDIO_AVAL_0960
#define SOR_AUDIO_AVAL_1920

#define SOR_INT_STATUS
#define SOR_INT_CODEC_CP_REQUEST
#define SOR_INT_CODEC_SCRATCH1
#define SOR_INT_CODEC_SCRATCH0

#define SOR_INT_MASK
#define SOR_INT_ENABLE

#define SOR_HDMI_VSI_INFOFRAME_CTRL
#define SOR_HDMI_VSI_INFOFRAME_STATUS
#define SOR_HDMI_VSI_INFOFRAME_HEADER

#define SOR_HDMI_AUDIO_N
#define SOR_HDMI_AUDIO_N_LOOKUP
#define SOR_HDMI_AUDIO_N_RESET

#define SOR_HDMI2_CTRL
#define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4
#define SOR_HDMI2_CTRL_SCRAMBLE

#endif