// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 NVIDIA Corporation */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/debugfs.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> #include <linux/reset.h> #include <soc/tegra/pmc.h> #include <drm/display/drm_dp_helper.h> #include <drm/display/drm_scdc_helper.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_debugfs.h> #include <drm/drm_edid.h> #include <drm/drm_eld.h> #include <drm/drm_file.h> #include <drm/drm_panel.h> #include <drm/drm_simple_kms_helper.h> #include "dc.h" #include "dp.h" #include "drm.h" #include "hda.h" #include "sor.h" #include "trace.h" #define SOR_REKEY … struct tegra_sor_hdmi_settings { … }; #if 1 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = …; #else static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { { .frequency = 75000000, .vcocap = 0x3, .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, .tmds_termadj = 0x9, .tx_pu_value = 0x40, .bg_temp_coef = 0x3, .bg_vref_level = 0x8, .avdd10_level = 0x4, .avdd14_level = 0x4, .sparepll = 0x0, .drive_current = { 0x29, 0x29, 0x29, 0x29 }, .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, }, { .frequency = 150000000, .vcocap = 0x3, .filter = 0x0, .ichpmp = 0x1, .loadadj = 0x3, .tmds_termadj = 0x9, .tx_pu_value = 0x66, .bg_temp_coef = 0x3, .bg_vref_level = 0x8, .avdd10_level = 0x4, .avdd14_level = 0x4, .sparepll = 0x0, .drive_current = { 0x30, 0x37, 0x37, 0x37 }, .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, }, { .frequency = 300000000, .vcocap = 0x3, .filter = 0x0, .ichpmp = 0x6, .loadadj = 0x3, .tmds_termadj = 0x9, .tx_pu_value = 0x66, .bg_temp_coef = 0x3, .bg_vref_level = 0xf, .avdd10_level = 0x4, .avdd14_level = 0x4, .sparepll = 0x0, .drive_current = { 0x30, 0x37, 0x37, 0x37 }, .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, }, { .frequency = 600000000, .vcocap = 0x3, .filter = 0x0, .ichpmp = 0xa, .loadadj = 0x3, .tmds_termadj = 0xb, .tx_pu_value = 0x66, .bg_temp_coef = 0x3, .bg_vref_level = 0xe, .avdd10_level = 0x4, .avdd14_level = 0x4, .sparepll = 0x0, .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, }, }; #endif static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = …; static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = …; struct tegra_sor_regs { … }; struct tegra_sor_soc { … }; struct tegra_sor; struct tegra_sor_ops { … }; struct tegra_sor { … }; struct tegra_sor_state { … }; static inline struct tegra_sor_state * to_sor_state(struct drm_connector_state *state) { … } struct tegra_sor_config { … }; static inline struct tegra_sor * host1x_client_to_sor(struct host1x_client *client) { … } static inline struct tegra_sor *to_sor(struct tegra_output *output) { … } static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) { … } static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, unsigned int offset) { … } static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) { … } struct tegra_clk_sor_pad { … }; static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) { … } static const char * const tegra_clk_sor_pad_parents[2][2] = …; /* * Implementing ->set_parent() here isn't really required because the parent * will be explicitly selected in the driver code via the DP_CLK_SEL mux in * the SOR_CLK_CNTRL register. This is primarily for compatibility with the * Tegra186 and later SoC generations where the BPMP implements this clock * and doesn't expose the mux via the common clock framework. */ static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) { … } static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) { … } static const struct clk_ops tegra_clk_sor_pad_ops = …; static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, const char *name) { … } static void tegra_sor_filter_rates(struct tegra_sor *sor) { … } static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) { … } static int tegra_sor_power_down_lanes(struct tegra_sor *sor) { … } static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) { … } static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) { … } static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) { … } static int tegra_sor_dp_link_configure(struct drm_dp_link *link) { … } static const struct drm_dp_link_ops tegra_sor_dp_link_ops = …; static void tegra_sor_super_update(struct tegra_sor *sor) { … } static void tegra_sor_update(struct tegra_sor *sor) { … } static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) { … } static int tegra_sor_attach(struct tegra_sor *sor) { … } static int tegra_sor_wakeup(struct tegra_sor *sor) { … } static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) { … } struct tegra_sor_params { … }; static int tegra_sor_compute_params(struct tegra_sor *sor, struct tegra_sor_params *params, unsigned int tu_size) { … } static int tegra_sor_compute_config(struct tegra_sor *sor, const struct drm_display_mode *mode, struct tegra_sor_config *config, struct drm_dp_link *link) { … } static void tegra_sor_apply_config(struct tegra_sor *sor, const struct tegra_sor_config *config) { … } static void tegra_sor_mode_set(struct tegra_sor *sor, const struct drm_display_mode *mode, struct tegra_sor_state *state) { … } static int tegra_sor_detach(struct tegra_sor *sor) { … } static int tegra_sor_power_down(struct tegra_sor *sor) { … } static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) { … } static int tegra_sor_show_crc(struct seq_file *s, void *data) { … } #define DEBUGFS_REG32(_name) … static const struct debugfs_reg32 tegra_sor_regs[] = …; static int tegra_sor_show_regs(struct seq_file *s, void *data) { … } static const struct drm_info_list debugfs_files[] = …; static int tegra_sor_late_register(struct drm_connector *connector) { … } static void tegra_sor_early_unregister(struct drm_connector *connector) { … } static void tegra_sor_connector_reset(struct drm_connector *connector) { … } static enum drm_connector_status tegra_sor_connector_detect(struct drm_connector *connector, bool force) { … } static struct drm_connector_state * tegra_sor_connector_duplicate_state(struct drm_connector *connector) { … } static const struct drm_connector_funcs tegra_sor_connector_funcs = …; static int tegra_sor_connector_get_modes(struct drm_connector *connector) { … } static enum drm_mode_status tegra_sor_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { … } static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = …; static int tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) { … } static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, const void *data, size_t size) { … } static int tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, const struct drm_display_mode *mode) { … } static void tegra_sor_write_eld(struct tegra_sor *sor) { … } static void tegra_sor_audio_prepare(struct tegra_sor *sor) { … } static void tegra_sor_audio_unprepare(struct tegra_sor *sor) { … } static void tegra_sor_audio_enable(struct tegra_sor *sor) { … } static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) { … } static struct tegra_sor_hdmi_settings * tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) { … } static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_scdc_work(struct work_struct *work) { … } static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) { … } static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) { … } static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) { … } static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = …; static void tegra_sor_dp_disable(struct drm_encoder *encoder) { … } static void tegra_sor_dp_enable(struct drm_encoder *encoder) { … } static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = …; static void tegra_sor_disable_regulator(void *data) { … } static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) { … } static int tegra_sor_hdmi_probe(struct tegra_sor *sor) { … } static const struct tegra_sor_ops tegra_sor_hdmi_ops = …; static int tegra_sor_dp_probe(struct tegra_sor *sor) { … } static const struct tegra_sor_ops tegra_sor_dp_ops = …; static int tegra_sor_init(struct host1x_client *client) { … } static int tegra_sor_exit(struct host1x_client *client) { … } static int tegra_sor_runtime_suspend(struct host1x_client *client) { … } static int tegra_sor_runtime_resume(struct host1x_client *client) { … } static const struct host1x_client_ops sor_client_ops = …; static const u8 tegra124_sor_xbar_cfg[5] = …; static const struct tegra_sor_regs tegra124_sor_regs = …; /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ static const u8 tegra124_sor_lane_map[4] = …; static const u8 tegra124_sor_voltage_swing[4][4][4] = …; static const u8 tegra124_sor_pre_emphasis[4][4][4] = …; static const u8 tegra124_sor_post_cursor[4][4][4] = …; static const u8 tegra124_sor_tx_pu[4][4][4] = …; static const struct tegra_sor_soc tegra124_sor = …; static const u8 tegra132_sor_pre_emphasis[4][4][4] = …; static const struct tegra_sor_soc tegra132_sor = …; static const struct tegra_sor_regs tegra210_sor_regs = …; static const u8 tegra210_sor_xbar_cfg[5] = …; static const u8 tegra210_sor_lane_map[4] = …; static const struct tegra_sor_soc tegra210_sor = …; static const struct tegra_sor_soc tegra210_sor1 = …; static const struct tegra_sor_regs tegra186_sor_regs = …; static const u8 tegra186_sor_voltage_swing[4][4][4] = …; static const u8 tegra186_sor_pre_emphasis[4][4][4] = …; static const struct tegra_sor_soc tegra186_sor = …; static const struct tegra_sor_regs tegra194_sor_regs = …; static const struct tegra_sor_soc tegra194_sor = …; static const struct of_device_id tegra_sor_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_sor_of_match); static int tegra_sor_parse_dt(struct tegra_sor *sor) { … } static irqreturn_t tegra_sor_irq(int irq, void *data) { … } static int tegra_sor_probe(struct platform_device *pdev) { … } static void tegra_sor_remove(struct platform_device *pdev) { … } static int __maybe_unused tegra_sor_suspend(struct device *dev) { … } static int __maybe_unused tegra_sor_resume(struct device *dev) { … } static const struct dev_pm_ops tegra_sor_pm_ops = …; struct platform_driver tegra_sor_driver = …;
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