linux/drivers/gpu/drm/tegra/dpaux.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 NVIDIA Corporation
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/workqueue.h>

#include <drm/display/drm_dp_helper.h>
#include <drm/display/drm_dp_aux_bus.h>
#include <drm/drm_panel.h>

#include "dp.h"
#include "dpaux.h"
#include "drm.h"
#include "trace.h"

static DEFINE_MUTEX(dpaux_lock);
static LIST_HEAD(dpaux_list);

struct tegra_dpaux_soc {};

struct tegra_dpaux {};

static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
{}

static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
{}

static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
				    unsigned int offset)
{}

static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
				      u32 value, unsigned int offset)
{}

static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
				   size_t size)
{}

static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
				  size_t size)
{}

static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
				    struct drm_dp_aux_msg *msg)
{}

static void tegra_dpaux_hotplug(struct work_struct *work)
{}

static irqreturn_t tegra_dpaux_irq(int irq, void *data)
{}

enum tegra_dpaux_functions {};

static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
{}

static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
{}

static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
{}

#ifdef CONFIG_GENERIC_PINCONF
static const struct pinctrl_pin_desc tegra_dpaux_pins[] =;

static const unsigned tegra_dpaux_pin_numbers[] =;

static const char * const tegra_dpaux_groups[] =;

static const char * const tegra_dpaux_functions[] =;

static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
{}

static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
					      unsigned int group)
{}

static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
				      unsigned group, const unsigned **pins,
				      unsigned *num_pins)
{}

static const struct pinctrl_ops tegra_dpaux_pinctrl_ops =;

static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
{}

static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
						 unsigned int function)
{}

static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
					   unsigned int function,
					   const char * const **groups,
					   unsigned * const num_groups)
{}

static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
			       unsigned int function, unsigned int group)
{}

static const struct pinmux_ops tegra_dpaux_pinmux_ops =;
#endif

static int tegra_dpaux_probe(struct platform_device *pdev)
{}

static void tegra_dpaux_remove(struct platform_device *pdev)
{}

static int tegra_dpaux_suspend(struct device *dev)
{}

static int tegra_dpaux_resume(struct device *dev)
{}

static const struct dev_pm_ops tegra_dpaux_pm_ops =;

static const struct tegra_dpaux_soc tegra124_dpaux_soc =;

static const struct tegra_dpaux_soc tegra210_dpaux_soc =;

static const struct tegra_dpaux_soc tegra194_dpaux_soc =;

static const struct of_device_id tegra_dpaux_of_match[] =;
MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);

struct platform_driver tegra_dpaux_driver =;

struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
{}

int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
{}

int drm_dp_aux_detach(struct drm_dp_aux *aux)
{}

enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
{}

int drm_dp_aux_enable(struct drm_dp_aux *aux)
{}

int drm_dp_aux_disable(struct drm_dp_aux *aux)
{}