/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2022, NVIDIA Corporation. */ #ifndef DRM_TEGRA_RISCV_H #define DRM_TEGRA_RISCV_H struct tegra_drm_riscv_descriptor { … }; struct tegra_drm_riscv { … }; int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv); int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, u32 gscid, const struct tegra_drm_riscv_descriptor *desc); #endif