linux/drivers/gpu/drm/tegra/riscv.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2022, NVIDIA Corporation.
 */

#include <linux/dev_printk.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/of.h>

#include "riscv.h"

#define RISCV_CPUCTL …
#define RISCV_CPUCTL_STARTCPU_TRUE …
#define RISCV_BR_RETCODE …
#define RISCV_BR_RETCODE_RESULT_V(x) …
#define RISCV_BR_RETCODE_RESULT_PASS_V …
#define RISCV_BCR_CTRL …
#define RISCV_BCR_CTRL_CORE_SELECT_RISCV …
#define RISCV_BCR_DMACFG …
#define RISCV_BCR_DMACFG_TARGET_LOCAL_FB …
#define RISCV_BCR_DMACFG_LOCK_LOCKED …
#define RISCV_BCR_DMAADDR_PKCPARAM_LO …
#define RISCV_BCR_DMAADDR_PKCPARAM_HI …
#define RISCV_BCR_DMAADDR_FMCCODE_LO …
#define RISCV_BCR_DMAADDR_FMCCODE_HI …
#define RISCV_BCR_DMAADDR_FMCDATA_LO …
#define RISCV_BCR_DMAADDR_FMCDATA_HI …
#define RISCV_BCR_DMACFG_SEC …
#define RISCV_BCR_DMACFG_SEC_GSCID(v) …

static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset)
{ … }

int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv)
{ … }

int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
				 u32 gscid, const struct tegra_drm_riscv_descriptor *desc)
{ … }