/* SPDX-License-Identifier: GPL-2.0 */ // // Ingenic JZ47xx IPU - Register definitions and private API // // Copyright (C) 2020, Paul Cercueil <[email protected]> #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H #define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H #include <linux/bitops.h> #define JZ_REG_IPU_CTRL … #define JZ_REG_IPU_STATUS … #define JZ_REG_IPU_D_FMT … #define JZ_REG_IPU_Y_ADDR … #define JZ_REG_IPU_U_ADDR … #define JZ_REG_IPU_V_ADDR … #define JZ_REG_IPU_IN_GS … #define JZ_REG_IPU_Y_STRIDE … #define JZ_REG_IPU_UV_STRIDE … #define JZ_REG_IPU_OUT_ADDR … #define JZ_REG_IPU_OUT_GS … #define JZ_REG_IPU_OUT_STRIDE … #define JZ_REG_IPU_RSZ_COEF_INDEX … #define JZ_REG_IPU_CSC_C0_COEF … #define JZ_REG_IPU_CSC_C1_COEF … #define JZ_REG_IPU_CSC_C2_COEF … #define JZ_REG_IPU_CSC_C3_COEF … #define JZ_REG_IPU_CSC_C4_COEF … #define JZ_REG_IPU_HRSZ_COEF_LUT … #define JZ_REG_IPU_VRSZ_COEF_LUT … #define JZ_REG_IPU_CSC_OFFSET … #define JZ_REG_IPU_Y_PHY_T_ADDR … #define JZ_REG_IPU_U_PHY_T_ADDR … #define JZ_REG_IPU_V_PHY_T_ADDR … #define JZ_REG_IPU_OUT_PHY_T_ADDR … #define JZ_IPU_CTRL_ADDR_SEL … #define JZ_IPU_CTRL_ZOOM_SEL … #define JZ_IPU_CTRL_DFIX_SEL … #define JZ_IPU_CTRL_LCDC_SEL … #define JZ_IPU_CTRL_SPKG_SEL … #define JZ_IPU_CTRL_VSCALE … #define JZ_IPU_CTRL_HSCALE … #define JZ_IPU_CTRL_STOP … #define JZ_IPU_CTRL_RST … #define JZ_IPU_CTRL_FM_IRQ_EN … #define JZ_IPU_CTRL_CSC_EN … #define JZ_IPU_CTRL_VRSZ_EN … #define JZ_IPU_CTRL_HRSZ_EN … #define JZ_IPU_CTRL_RUN … #define JZ_IPU_CTRL_CHIP_EN … #define JZ_IPU_STATUS_OUT_END … #define JZ_IPU_IN_GS_H_LSB … #define JZ_IPU_IN_GS_W_LSB … #define JZ_IPU_OUT_GS_H_LSB … #define JZ_IPU_OUT_GS_W_LSB … #define JZ_IPU_Y_STRIDE_Y_LSB … #define JZ_IPU_UV_STRIDE_U_LSB … #define JZ_IPU_UV_STRIDE_V_LSB … #define JZ_IPU_D_FMT_IN_FMT_LSB … #define JZ_IPU_D_FMT_IN_FMT_RGB555 … #define JZ_IPU_D_FMT_IN_FMT_YUV420 … #define JZ_IPU_D_FMT_IN_FMT_YUV422 … #define JZ_IPU_D_FMT_IN_FMT_RGB888 … #define JZ_IPU_D_FMT_IN_FMT_YUV444 … #define JZ_IPU_D_FMT_IN_FMT_RGB565 … #define JZ_IPU_D_FMT_YUV_FMT_LSB … #define JZ_IPU_D_FMT_YUV_Y1UY0V … #define JZ_IPU_D_FMT_YUV_Y1VY0U … #define JZ_IPU_D_FMT_YUV_UY1VY0 … #define JZ_IPU_D_FMT_YUV_VY1UY0 … #define JZ_IPU_D_FMT_IN_FMT_YUV411 … #define JZ_IPU_D_FMT_OUT_FMT_LSB … #define JZ_IPU_D_FMT_OUT_FMT_RGB555 … #define JZ_IPU_D_FMT_OUT_FMT_RGB565 … #define JZ_IPU_D_FMT_OUT_FMT_RGB888 … #define JZ_IPU_D_FMT_OUT_FMT_YUV422 … #define JZ_IPU_D_FMT_OUT_FMT_RGBAAA … #define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB … #define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB … #define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG … #define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR … #define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB … #define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG … #define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR … #define JZ4725B_IPU_RSZ_LUT_COEF_LSB … #define JZ4725B_IPU_RSZ_LUT_COEF_MASK … #define JZ4725B_IPU_RSZ_LUT_IN_EN … #define JZ4725B_IPU_RSZ_LUT_OUT_EN … #define JZ4760_IPU_RSZ_COEF20_LSB … #define JZ4760_IPU_RSZ_COEF31_LSB … #define JZ4760_IPU_RSZ_COEF_MASK … #define JZ4760_IPU_RSZ_OFFSET_LSB … #define JZ4760_IPU_RSZ_OFFSET_MASK … #define JZ_IPU_CSC_OFFSET_CHROMA_LSB … #define JZ_IPU_CSC_OFFSET_LUMA_LSB … #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */
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