/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright(c) 2016, Analogix Semiconductor. * * Based on anx7808 driver obtained from chromeos with copyright: * Copyright(c) 2013, Google Inc. */ #ifndef _ANALOGIX_I2C_DPTX_H_ #define _ANALOGIX_I2C_DPTX_H_ /***************************************************************/ /* Register definitions for TX_P0 */ /***************************************************************/ /* HDCP Status Register */ #define SP_TX_HDCP_STATUS_REG … #define SP_AUTH_FAIL … #define SP_AUTHEN_PASS … /* HDCP Control Register 0 */ #define SP_HDCP_CTRL0_REG … #define SP_RX_REPEATER … #define SP_RE_AUTH … #define SP_SW_AUTH_OK … #define SP_HARD_AUTH_EN … #define SP_HDCP_ENC_EN … #define SP_BKSV_SRM_PASS … #define SP_KSVLIST_VLD … /* HDCP Function Enabled */ #define SP_HDCP_FUNCTION_ENABLED … /* HDCP Receiver BSTATUS Register 0 */ #define SP_HDCP_RX_BSTATUS0_REG … /* HDCP Receiver BSTATUS Register 1 */ #define SP_HDCP_RX_BSTATUS1_REG … /* HDCP Embedded "Blue Screen" Content Registers */ #define SP_HDCP_VID0_BLUE_SCREEN_REG … #define SP_HDCP_VID1_BLUE_SCREEN_REG … #define SP_HDCP_VID2_BLUE_SCREEN_REG … /* HDCP Wait R0 Timing Register */ #define SP_HDCP_WAIT_R0_TIME_REG … /* HDCP Link Integrity Check Timer Register */ #define SP_HDCP_LINK_CHECK_TIMER_REG … /* HDCP Repeater Ready Wait Timer Register */ #define SP_HDCP_RPTR_RDY_WAIT_TIME_REG … /* HDCP Auto Timer Register */ #define SP_HDCP_AUTO_TIMER_REG … /* HDCP Key Status Register */ #define SP_HDCP_KEY_STATUS_REG … /* HDCP Key Command Register */ #define SP_HDCP_KEY_COMMAND_REG … #define SP_DISABLE_SYNC_HDCP … /* OTP Memory Key Protection Registers */ #define SP_OTP_KEY_PROTECT1_REG … #define SP_OTP_KEY_PROTECT2_REG … #define SP_OTP_KEY_PROTECT3_REG … #define SP_OTP_PSW1 … #define SP_OTP_PSW2 … #define SP_OTP_PSW3 … /* DP System Control Registers */ #define SP_DP_SYSTEM_CTRL_BASE … /* Bits for DP System Control Register 2 */ #define SP_CHA_STA … /* Bits for DP System Control Register 3 */ #define SP_HPD_STATUS … #define SP_HPD_FORCE … #define SP_HPD_CTRL … #define SP_STRM_VALID … #define SP_STRM_FORCE … #define SP_STRM_CTRL … /* Bits for DP System Control Register 4 */ #define SP_ENHANCED_MODE … /* DP Video Control Register */ #define SP_DP_VIDEO_CTRL_REG … #define SP_COLOR_F_MASK … #define SP_COLOR_F_SHIFT … #define SP_BPC_MASK … #define SP_BPC_SHIFT … #define SP_BPC_6BITS … #define SP_BPC_8BITS … #define SP_BPC_10BITS … #define SP_BPC_12BITS … /* DP Audio Control Register */ #define SP_DP_AUDIO_CTRL_REG … #define SP_AUD_EN … /* 10us Pulse Generate Timer Registers */ #define SP_I2C_GEN_10US_TIMER0_REG … #define SP_I2C_GEN_10US_TIMER1_REG … /* Packet Send Control Register */ #define SP_PACKET_SEND_CTRL_REG … #define SP_AUD_IF_UP … #define SP_AVI_IF_UD … #define SP_MPEG_IF_UD … #define SP_SPD_IF_UD … #define SP_AUD_IF_EN … #define SP_AVI_IF_EN … #define SP_MPEG_IF_EN … #define SP_SPD_IF_EN … /* DP HDCP Control Register */ #define SP_DP_HDCP_CTRL_REG … #define SP_AUTO_EN … #define SP_AUTO_START … #define SP_LINK_POLLING … /* DP Main Link Bandwidth Setting Register */ #define SP_DP_MAIN_LINK_BW_SET_REG … #define SP_LINK_BW_SET_MASK … #define SP_INITIAL_SLIM_M_AUD_SEL … /* DP Lane Count Setting Register */ #define SP_DP_LANE_COUNT_SET_REG … /* DP Training Pattern Set Register */ #define SP_DP_TRAINING_PATTERN_SET_REG … /* DP Lane 0 Link Training Control Register */ #define SP_DP_LANE0_LT_CTRL_REG … #define SP_TX_SW_SET_MASK … #define SP_MAX_PRE_REACH … #define SP_MAX_DRIVE_REACH … #define SP_PRE_EMP_LEVEL1 … #define SP_DRVIE_CURRENT_LEVEL1 … /* DP Link Training Control Register */ #define SP_DP_LT_CTRL_REG … #define SP_DP_LT_INPROGRESS … #define SP_LT_ERROR_TYPE_MASK … #define SP_LT_NO_ERROR … #define SP_LT_AUX_WRITE_ERROR … #define SP_LT_MAX_DRIVE_REACHED … #define SP_LT_WRONG_LANE_COUNT_SET … #define SP_LT_LOOP_SAME_5_TIME … #define SP_LT_CR_FAIL_IN_EQ … #define SP_LT_EQ_LOOP_5_TIME … #define SP_LT_EN … /* DP CEP Training Control Registers */ #define SP_DP_CEP_TRAINING_CTRL0_REG … #define SP_DP_CEP_TRAINING_CTRL1_REG … /* DP Debug Register 1 */ #define SP_DP_DEBUG1_REG … #define SP_DEBUG_PLL_LOCK … #define SP_POLLING_EN … /* DP Polling Control Register */ #define SP_DP_POLLING_CTRL_REG … #define SP_AUTO_POLLING_DISABLE … /* DP Link Debug Control Register */ #define SP_DP_LINK_DEBUG_CTRL_REG … #define SP_M_VID_DEBUG … #define SP_NEW_PRBS7 … #define SP_INSERT_ER … #define SP_PRBS31_EN … /* AUX Misc control Register */ #define SP_AUX_MISC_CTRL_REG … /* DP PLL control Register */ #define SP_DP_PLL_CTRL_REG … #define SP_PLL_RST … /* DP Analog Power Down Register */ #define SP_DP_ANALOG_POWER_DOWN_REG … #define SP_CH0_PD … /* DP Misc Control Register */ #define SP_DP_MISC_CTRL_REG … #define SP_EQ_TRAINING_LOOP … /* DP Extra I2C Device Address Register */ #define SP_DP_EXTRA_I2C_DEV_ADDR_REG … #define SP_I2C_STRETCH_DISABLE … #define SP_I2C_EXTRA_ADDR … /* DP Downspread Control Register 1 */ #define SP_DP_DOWNSPREAD_CTRL1_REG … /* DP M Value Calculation Control Register */ #define SP_DP_M_CALCULATION_CTRL_REG … #define SP_M_GEN_CLK_SEL … /* AUX Channel Access Status Register */ #define SP_AUX_CH_STATUS_REG … #define SP_AUX_STATUS … /* AUX Channel DEFER Control Register */ #define SP_AUX_DEFER_CTRL_REG … #define SP_DEFER_CTRL_EN … /* DP Buffer Data Count Register */ #define SP_BUF_DATA_COUNT_REG … #define SP_BUF_DATA_COUNT_MASK … #define SP_BUF_CLR … /* DP AUX Channel Control Register 1 */ #define SP_DP_AUX_CH_CTRL1_REG … #define SP_AUX_TX_COMM_MASK … #define SP_AUX_LENGTH_MASK … #define SP_AUX_LENGTH_SHIFT … /* DP AUX CH Address Register 0 */ #define SP_AUX_ADDR_7_0_REG … /* DP AUX CH Address Register 1 */ #define SP_AUX_ADDR_15_8_REG … /* DP AUX CH Address Register 2 */ #define SP_AUX_ADDR_19_16_REG … #define SP_AUX_ADDR_19_16_MASK … /* DP AUX Channel Control Register 2 */ #define SP_DP_AUX_CH_CTRL2_REG … #define SP_AUX_SEL_RXCM … #define SP_AUX_CHSEL … #define SP_AUX_PN_INV … #define SP_ADDR_ONLY … #define SP_AUX_EN … /* DP Video Stream Control InfoFrame Register */ #define SP_DP_3D_VSC_CTRL_REG … #define SP_INFO_FRAME_VSC_EN … /* DP Video Stream Data Byte 1 Register */ #define SP_DP_VSC_DB1_REG … /* DP AUX Channel Control Register 3 */ #define SP_DP_AUX_CH_CTRL3_REG … #define SP_WAIT_COUNTER_7_0_MASK … /* DP AUX Channel Control Register 4 */ #define SP_DP_AUX_CH_CTRL4_REG … /* DP AUX Buffer Data Registers */ #define SP_DP_BUF_DATA0_REG … ssize_t anx_dp_aux_transfer(struct regmap *map_dptx, struct drm_dp_aux_msg *msg); #endif
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