/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. * */ #ifndef __ANX7625_H__ #define __ANX7625_H__ #define ANX7625_DRV_VERSION … /* Loading OCM re-trying times */ #define OCM_LOADING_TIME … /********* ANX7625 Register **********/ #define TX_P0_ADDR … #define TX_P1_ADDR … #define TX_P2_ADDR … #define RX_P0_ADDR … #define RX_P1_ADDR … #define RX_P2_ADDR … #define RSVD_00_ADDR … #define RSVD_D1_ADDR … #define RSVD_60_ADDR … #define RSVD_39_ADDR … #define RSVD_7F_ADDR … #define TCPC_INTERFACE_ADDR … /* Clock frequency in Hz */ #define XTAL_FRQ … #define POST_DIVIDER_MIN … #define POST_DIVIDER_MAX … #define PLL_OUT_FREQ_MIN … #define PLL_OUT_FREQ_MAX … #define PLL_OUT_FREQ_ABS_MIN … #define PLL_OUT_FREQ_ABS_MAX … #define MAX_UNSIGNED_24BIT … /***************************************************************/ /* Register definition of device address 0x58 */ #define PRODUCT_ID_L … #define PRODUCT_ID_H … #define INTR_ALERT_1 … #define INTR_SOFTWARE_INT … #define INTR_RECEIVED_MSG … #define SYSTEM_STSTUS … #define INTERFACE_CHANGE_INT … #define HPD_STATUS_CHANGE … #define HPD_STATUS … /******** END of I2C Address 0x58 ********/ /***************************************************************/ /* Register definition of device address 0x70 */ #define TX_HDCP_CTRL0 … #define STORE_AN … #define RX_REPEATER … #define RE_AUTHEN … #define SW_AUTH_OK … #define HARD_AUTH_EN … #define ENC_EN … #define BKSV_SRM_PASS … #define KSVLIST_VLD … #define SP_TX_WAIT_R0_TIME … #define SP_TX_WAIT_KSVR_TIME … #define SP_TX_SYS_CTRL1_REG … #define HDCP2TX_FW_EN … #define SP_TX_LINK_BW_SET_REG … #define SP_TX_LANE_COUNT_SET_REG … #define M_VID_0 … #define M_VID_1 … #define M_VID_2 … #define N_VID_0 … #define N_VID_1 … #define N_VID_2 … #define KEY_START_ADDR … #define KEY_RESERVED … #define HDCP14KEY_START_ADDR … #define HDCP14KEY_SIZE … /***************************************************************/ /* Register definition of device address 0x72 */ #define AUX_RST … #define RST_CTRL2 … #define SP_TX_TOTAL_LINE_STA_L … #define SP_TX_TOTAL_LINE_STA_H … #define SP_TX_ACT_LINE_STA_L … #define SP_TX_ACT_LINE_STA_H … #define SP_TX_V_F_PORCH_STA … #define SP_TX_V_SYNC_STA … #define SP_TX_V_B_PORCH_STA … #define SP_TX_TOTAL_PIXEL_STA_L … #define SP_TX_TOTAL_PIXEL_STA_H … #define SP_TX_ACT_PIXEL_STA_L … #define SP_TX_ACT_PIXEL_STA_H … #define SP_TX_H_F_PORCH_STA_L … #define SP_TX_H_F_PORCH_STA_H … #define SP_TX_H_SYNC_STA_L … #define SP_TX_H_SYNC_STA_H … #define SP_TX_H_B_PORCH_STA_L … #define SP_TX_H_B_PORCH_STA_H … #define SP_TX_VID_CTRL … #define SP_TX_BPC_MASK … #define SP_TX_BPC_6 … #define SP_TX_BPC_8 … #define SP_TX_BPC_10 … #define SP_TX_BPC_12 … #define VIDEO_BIT_MATRIX_12 … #define AUDIO_CHANNEL_STATUS_1 … #define AUDIO_CHANNEL_STATUS_2 … #define AUDIO_CHANNEL_STATUS_3 … #define AUDIO_CHANNEL_STATUS_4 … #define AUDIO_CHANNEL_STATUS_5 … #define AUDIO_CHANNEL_STATUS_6 … #define TDM_SLAVE_MODE … #define I2S_SLAVE_MODE … #define AUDIO_LAYOUT … #define HPD_DET_TIMER_BIT0_7 … #define HPD_DET_TIMER_BIT8_15 … #define HPD_DET_TIMER_BIT16_23 … /* HPD debounce time 2ms for 27M clock */ #define HPD_TIME … #define AUDIO_CONTROL_REGISTER … #define TDM_TIMING_MODE … #define I2C_ADDR_72_DPTX … #define HP_MIN … #define HBLANKING_MIN … #define SYNC_LEN_DEF … #define HFP_HBP_DEF … #define VIDEO_CONTROL_0 … #define ACTIVE_LINES_L … #define ACTIVE_LINES_H … #define VERTICAL_FRONT_PORCH … #define VERTICAL_SYNC_WIDTH … #define VERTICAL_BACK_PORCH … #define HORIZONTAL_TOTAL_PIXELS_L … #define HORIZONTAL_TOTAL_PIXELS_H … #define HORIZONTAL_ACTIVE_PIXELS_L … #define HORIZONTAL_ACTIVE_PIXELS_H … #define HORIZONTAL_FRONT_PORCH_L … #define HORIZONTAL_FRONT_PORCH_H … #define HORIZONTAL_SYNC_WIDTH_L … #define HORIZONTAL_SYNC_WIDTH_H … #define HORIZONTAL_BACK_PORCH_L … #define HORIZONTAL_BACK_PORCH_H … /******** END of I2C Address 0x72 *********/ /***************************************************************/ /* Register definition of device address 0x7a */ #define DP_TX_SWING_REG_CNT … #define DP_TX_LANE0_SWING_REG0 … #define DP_TX_LANE1_SWING_REG0 … /******** END of I2C Address 0x7a *********/ /***************************************************************/ /* Register definition of device address 0x7e */ #define I2C_ADDR_7E_FLASH_CONTROLLER … #define R_BOOT_RETRY … #define R_RAM_ADDR_H … #define R_RAM_ADDR_L … #define R_RAM_LEN_H … #define R_RAM_LEN_L … #define FLASH_LOAD_STA … #define FLASH_LOAD_STA_CHK … #define R_RAM_CTRL … /* bit positions */ #define FLASH_DONE … #define BOOT_LOAD_DONE … #define CRC_OK … #define LOAD_DONE … #define O_RW_DONE … #define FUSE_BUSY … #define DECRYPT_EN … #define LOAD_START … #define FLASH_ADDR_HIGH … #define FLASH_ADDR_LOW … #define FLASH_LEN_HIGH … #define FLASH_LEN_LOW … #define R_FLASH_RW_CTRL … /* bit positions */ #define READ_DELAY_SELECT … #define GENERAL_INSTRUCTION_EN … #define FLASH_ERASE_EN … #define RDID_READ_EN … #define REMS_READ_EN … #define WRITE_STATUS_EN … #define FLASH_READ … #define FLASH_WRITE … #define FLASH_BUF_BASE_ADDR … #define FLASH_BUF_LEN … #define XTAL_FRQ_SEL … /* bit field positions */ #define XTAL_FRQ_SEL_POS … /* bit field values */ #define XTAL_FRQ_19M2 … #define XTAL_FRQ_27M … #define R_DSC_CTRL_0 … #define READ_STATUS_EN … #define CLK_1MEG_RB … #define DSC_BIST_DONE … #define DSC_EN … #define OCM_FW_VERSION … #define OCM_FW_REVERSION … #define AP_AUX_ADDR_7_0 … #define AP_AUX_ADDR_15_8 … #define AP_AUX_ADDR_19_16 … /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ #define AP_AUX_CTRL_STATUS … #define AP_AUX_CTRL_OP_EN … #define AP_AUX_CTRL_ADDRONLY … #define AP_AUX_BUFF_START … #define PIXEL_CLOCK_L … #define PIXEL_CLOCK_H … #define AP_AUX_COMMAND … #define LENGTH_SHIFT … #define DPCD_CMD(len, cmd) … /* Bit 0&1: 3D video structure */ /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ #define AP_AV_STATUS … #define AP_VIDEO_CHG … #define AP_AUDIO_CHG … #define AP_MIPI_MUTE … #define AP_MIPI_RX_EN … #define AP_DISABLE_PD … #define AP_DISABLE_DISPLAY … #define GPIO_CTRL_2 … #define HPD_SOURCE … /***************************************************************/ /* Register definition of device address 0x84 */ #define MIPI_PHY_CONTROL_3 … #define MIPI_HS_PWD_CLK … #define MIPI_HS_RT_CLK … #define MIPI_PD_CLK … #define MIPI_CLK_RT_MANUAL_PD_EN … #define MIPI_CLK_HS_MANUAL_PD_EN … #define MIPI_CLK_DET_DET_BYPASS … #define MIPI_CLK_MISS_CTRL … #define MIPI_PD_LPTX_CH_MANUAL_PD_EN … #define MIPI_LANE_CTRL_0 … #define MIPI_TIME_HS_PRPR … /* * After MIPI RX protocol layer received video frames, * Protocol layer starts to reconstruct video stream from PHY */ #define MIPI_VIDEO_STABLE_CNT … #define MIPI_LANE_CTRL_10 … #define MIPI_DIGITAL_ADJ_1 … #define IVO_MID … #define MIPI_PLL_M_NUM_23_16 … #define MIPI_PLL_M_NUM_15_8 … #define MIPI_PLL_M_NUM_7_0 … #define MIPI_PLL_N_NUM_23_16 … #define MIPI_PLL_N_NUM_15_8 … #define MIPI_PLL_N_NUM_7_0 … #define MIPI_DIGITAL_PLL_6 … /* Bit[7:6]: VCO band control, only effective */ #define MIPI_M_NUM_READY … #define MIPI_N_NUM_READY … #define STABLE_INTEGER_CNT_EN … #define MIPI_PLL_TEST_BIT … /* Bit[1:0]: test point output select - */ /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ #define MIPI_DIGITAL_PLL_7 … #define MIPI_PLL_FORCE_N_EN … #define MIPI_PLL_FORCE_BAND_EN … #define MIPI_PLL_VCO_TUNE_REG … /* Bit[5:4]: VCO metal capacitance - */ /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ #define MIPI_PLL_VCO_TUNE_REG_VAL … #define MIPI_PLL_PLL_LDO_BIT … /* Bit[3:2]: vco_v2i power - */ /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ #define MIPI_PLL_RESET_N … #define MIPI_FRQ_FORCE_NDET … #define MIPI_ALERT_CLR_0 … #define HS_link_error_clear … /* This bit itself is S/C, and it clears 0x84:0x31[7] */ #define MIPI_ALERT_OUT_0 … #define check_sum_err_hs_sync … /* This bit is cleared by 0x84:0x2D[7] */ #define MIPI_DIGITAL_PLL_8 … #define MIPI_POST_DIV_VAL … /* N means divided by (n+1), n = 0~15 */ #define MIPI_EN_LOCK_FRZ … #define MIPI_FRQ_COUNTER_RST … #define MIPI_FRQ_SET_REG_8 … /* Bit 0 is reserved */ #define MIPI_DIGITAL_PLL_9 … #define MIPI_DIGITAL_PLL_16 … #define MIPI_FRQ_FREEZE_NDET … #define MIPI_FRQ_REG_SET_ENABLE … #define MIPI_REG_FORCE_SEL_EN … #define MIPI_REG_SEL_DIV_REG … #define MIPI_REG_FORCE_PRE_DIV_EN … /* Bit 2 is reserved */ #define MIPI_FREF_D_IND … #define REF_CLK_27000KHZ … #define REF_CLK_19200KHZ … #define MIPI_REG_PLL_PLL_TEST_ENABLE … #define MIPI_DIGITAL_PLL_18 … #define FRQ_COUNT_RB_SEL … #define REG_FORCE_POST_DIV_EN … #define MIPI_DPI_SELECT … #define SELECT_DSI … #define SELECT_DPI … #define REG_BAUD_DIV_RATIO … #define H_BLANK_L … /* For DSC only */ #define H_BLANK_H … /* For DSC only; note: bit[7:6] are reserved */ #define MIPI_SWAP … #define MIPI_SWAP_CH0 … #define MIPI_SWAP_CH1 … #define MIPI_SWAP_CH2 … #define MIPI_SWAP_CH3 … #define MIPI_SWAP_CLK … /* Bit[2:0] are reserved */ /******** END of I2C Address 0x84 *********/ /* DPCD regs */ #define DPCD_DPCD_REV … #define DPCD_MAX_LINK_RATE … #define DPCD_MAX_LANE_COUNT … /********* ANX7625 Register End **********/ /***************** Display *****************/ enum audio_fs { … }; enum audio_wd_len { … }; #define I2S_CH_2 … #define TDM_CH_4 … #define TDM_CH_6 … #define TDM_CH_8 … #define MAX_DPCD_BUFFER_SIZE … #define ONE_BLOCK_SIZE … #define FOUR_BLOCK_SIZE … #define MAX_EDID_BLOCK … #define EDID_TRY_CNT … #define SUPPORT_PIXEL_CLOCK … /***************** Display End *****************/ #define MAX_LANES_SUPPORT … struct anx7625_platform_data { … }; struct anx7625_i2c_client { … }; struct anx7625_data { … }; #endif /* __ANX7625_H__ */
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