/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. */ #ifndef _ANALOGIX_I2C_TXCOMMON_H_ #define _ANALOGIX_I2C_TXCOMMON_H_ /***************************************************************/ /* Register definitions for TX_P2 */ /***************************************************************/ /* * Core Register Definitions */ /* Device ID Low Byte Register */ #define SP_DEVICE_IDL_REG … /* Device ID High Byte Register */ #define SP_DEVICE_IDH_REG … /* Device version register */ #define SP_DEVICE_VERSION_REG … /* Power Down Control Register */ #define SP_POWERDOWN_CTRL_REG … #define SP_REGISTER_PD … #define SP_HDCP_PD … #define SP_AUDIO_PD … #define SP_VIDEO_PD … #define SP_LINK_PD … #define SP_TOTAL_PD … /* Reset Control Register 1 */ #define SP_RESET_CTRL1_REG … #define SP_MISC_RST … #define SP_VIDCAP_RST … #define SP_VIDFIF_RST … #define SP_AUDFIF_RST … #define SP_AUDCAP_RST … #define SP_HDCP_RST … #define SP_SW_RST … #define SP_HW_RST … /* Reset Control Register 2 */ #define SP_RESET_CTRL2_REG … #define SP_AUX_RST … #define SP_SERDES_FIFO_RST … #define SP_I2C_REG_RST … /* Video Control Register 1 */ #define SP_VID_CTRL1_REG … #define SP_VIDEO_EN … #define SP_VIDEO_MUTE … #define SP_DE_GEN … #define SP_DEMUX … /* Video Control Register 2 */ #define SP_VID_CTRL2_REG … #define SP_IN_COLOR_F_MASK … #define SP_IN_YC_BIT_SEL … #define SP_IN_BPC_MASK … #define SP_IN_BPC_SHIFT … #define SP_IN_BPC_12BIT … #define SP_IN_BPC_10BIT … #define SP_IN_BPC_8BIT … #define SP_IN_BPC_6BIT … #define SP_IN_D_RANGE … /* Video Control Register 3 */ #define SP_VID_CTRL3_REG … #define SP_HPD_OUT … /* Video Control Register 5 */ #define SP_VID_CTRL5_REG … #define SP_CSC_STD_SEL … #define SP_XVYCC_RNG_LMT … #define SP_RANGE_Y2R … #define SP_CSPACE_Y2R … #define SP_RGB_RNG_LMT … #define SP_Y_RNG_LMT … #define SP_RANGE_R2Y … #define SP_CSPACE_R2Y … /* Video Control Register 6 */ #define SP_VID_CTRL6_REG … #define SP_TEST_PATTERN_EN … #define SP_VIDEO_PROCESS_EN … #define SP_VID_US_MODE … #define SP_VID_DS_MODE … #define SP_UP_SAMPLE … #define SP_DOWN_SAMPLE … /* Video Control Register 8 */ #define SP_VID_CTRL8_REG … #define SP_VID_VRES_TH … /* Total Line Status Low Byte Register */ #define SP_TOTAL_LINE_STAL_REG … /* Total Line Status High Byte Register */ #define SP_TOTAL_LINE_STAH_REG … /* Active Line Status Low Byte Register */ #define SP_ACT_LINE_STAL_REG … /* Active Line Status High Byte Register */ #define SP_ACT_LINE_STAH_REG … /* Vertical Front Porch Status Register */ #define SP_V_F_PORCH_STA_REG … /* Vertical SYNC Width Status Register */ #define SP_V_SYNC_STA_REG … /* Vertical Back Porch Status Register */ #define SP_V_B_PORCH_STA_REG … /* Total Pixel Status Low Byte Register */ #define SP_TOTAL_PIXEL_STAL_REG … /* Total Pixel Status High Byte Register */ #define SP_TOTAL_PIXEL_STAH_REG … /* Active Pixel Status Low Byte Register */ #define SP_ACT_PIXEL_STAL_REG … /* Active Pixel Status High Byte Register */ #define SP_ACT_PIXEL_STAH_REG … /* Horizontal Front Porch Status Low Byte Register */ #define SP_H_F_PORCH_STAL_REG … /* Horizontal Front Porch Statys High Byte Register */ #define SP_H_F_PORCH_STAH_REG … /* Horizontal SYNC Width Status Low Byte Register */ #define SP_H_SYNC_STAL_REG … /* Horizontal SYNC Width Status High Byte Register */ #define SP_H_SYNC_STAH_REG … /* Horizontal Back Porch Status Low Byte Register */ #define SP_H_B_PORCH_STAL_REG … /* Horizontal Back Porch Status High Byte Register */ #define SP_H_B_PORCH_STAH_REG … /* InfoFrame AVI Packet DB1 Register */ #define SP_INFOFRAME_AVI_DB1_REG … /* Bit Control Specific Register */ #define SP_BIT_CTRL_SPECIFIC_REG … #define SP_BIT_CTRL_SELECT_SHIFT … #define SP_ENABLE_BIT_CTRL … /* InfoFrame Audio Packet DB1 Register */ #define SP_INFOFRAME_AUD_DB1_REG … /* InfoFrame MPEG Packet DB1 Register */ #define SP_INFOFRAME_MPEG_DB1_REG … /* Audio Channel Status Registers */ #define SP_AUD_CH_STATUS_BASE … /* Audio Channel Num Register 5 */ #define SP_I2S_CHANNEL_NUM_MASK … #define SP_I2S_CH_NUM_1 … #define SP_I2S_CH_NUM_2 … #define SP_I2S_CH_NUM_3 … #define SP_I2S_CH_NUM_4 … #define SP_I2S_CH_NUM_5 … #define SP_I2S_CH_NUM_6 … #define SP_I2S_CH_NUM_7 … #define SP_I2S_CH_NUM_8 … #define SP_EXT_VUCP … #define SP_VBIT … #define SP_AUDIO_LAYOUT … /* Analog Debug Register 1 */ #define SP_ANALOG_DEBUG1_REG … /* Analog Debug Register 2 */ #define SP_ANALOG_DEBUG2_REG … #define SP_FORCE_SW_OFF_BYPASS … #define SP_XTAL_FRQ … #define SP_XTAL_FRQ_19M2 … #define SP_XTAL_FRQ_24M … #define SP_XTAL_FRQ_25M … #define SP_XTAL_FRQ_26M … #define SP_XTAL_FRQ_27M … #define SP_XTAL_FRQ_38M4 … #define SP_XTAL_FRQ_52M … #define SP_POWERON_TIME_1P5MS … /* Analog Control 0 Register */ #define SP_ANALOG_CTRL0_REG … /* Common Interrupt Status Register 1 */ #define SP_COMMON_INT_STATUS_BASE … #define SP_PLL_LOCK_CHG … /* Common Interrupt Status Register 2 */ #define SP_COMMON_INT_STATUS2 … #define SP_HDCP_AUTH_CHG … #define SP_HDCP_AUTH_DONE … #define SP_HDCP_LINK_CHECK_FAIL … /* Common Interrupt Status Register 4 */ #define SP_COMMON_INT_STATUS4_REG … #define SP_HPD_IRQ … #define SP_HPD_ESYNC_ERR … #define SP_HPD_CHG … #define SP_HPD_LOST … #define SP_HPD_PLUG … /* DP Interrupt Status Register */ #define SP_DP_INT_STATUS1_REG … #define SP_TRAINING_FINISH … #define SP_POLLING_ERR … /* Common Interrupt Mask Register */ #define SP_COMMON_INT_MASK_BASE … #define SP_COMMON_INT_MASK4_REG … /* DP Interrupts Mask Register */ #define SP_DP_INT_MASK1_REG … /* Interrupt Control Register */ #define SP_INT_CTRL_REG … #endif /* _ANALOGIX_I2C_TXCOMMON_H_ */
Codebase Browser
linux