/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. */ #ifndef __ANX78xx_H #define __ANX78xx_H #include "analogix-i2c-dptx.h" #include "analogix-i2c-txcommon.h" /***************************************************************/ /* Register definitions for RX_PO */ /***************************************************************/ /* * System Control and Status */ /* Software Reset Register 1 */ #define SP_SOFTWARE_RESET1_REG … #define SP_VIDEO_RST … #define SP_HDCP_MAN_RST … #define SP_TMDS_RST … #define SP_SW_MAN_RST … /* System Status Register */ #define SP_SYSTEM_STATUS_REG … #define SP_TMDS_CLOCK_DET … #define SP_TMDS_DE_DET … /* HDMI Status Register */ #define SP_HDMI_STATUS_REG … #define SP_HDMI_AUD_LAYOUT … #define SP_HDMI_DET … #define SP_DVI_MODE … #define SP_HDMI_MODE … /* HDMI Mute Control Register */ #define SP_HDMI_MUTE_CTRL_REG … #define SP_AUD_MUTE … #define SP_VID_MUTE … /* System Power Down Register 1 */ #define SP_SYSTEM_POWER_DOWN1_REG … #define SP_PWDN_CTRL … /* * Audio and Video Auto Control */ /* Auto Audio and Video Control register */ #define SP_AUDVID_CTRL_REG … #define SP_AVC_OE … #define SP_AAC_OE … #define SP_AVC_EN … #define SP_AAC_EN … /* Audio Exception Enable Registers */ #define SP_AUD_EXCEPTION_ENABLE_BASE … /* Bits for Audio Exception Enable Register 3 */ #define SP_AEC_EN21 … /* * Interrupt */ /* Interrupt Status Register 1 */ #define SP_INT_STATUS1_REG … /* Bits for Interrupt Status Register 1 */ #define SP_HDMI_DVI … #define SP_CKDT_CHG … #define SP_SCDT_CHG … #define SP_PCLK_CHG … #define SP_PLL_UNLOCK … #define SP_CABLE_PLUG_CHG … #define SP_SET_MUTE … #define SP_SW_INTR … /* Bits for Interrupt Status Register 2 */ #define SP_HDCP_ERR … #define SP_AUDIO_SAMPLE_CHG … /* Bits for Interrupt Status Register 3 */ #define SP_AUD_MODE_CHG … /* Bits for Interrupt Status Register 5 */ #define SP_AUDIO_RCV … /* Bits for Interrupt Status Register 6 */ #define SP_INT_STATUS6_REG … #define SP_CTS_RCV … #define SP_NEW_AUD_PKT … #define SP_NEW_AVI_PKT … #define SP_NEW_CP_PKT … /* Bits for Interrupt Status Register 7 */ #define SP_NO_VSI … #define SP_NEW_VS … /* Interrupt Mask 1 Status Registers */ #define SP_INT_MASK1_REG … /* HDMI US TIMER Control Register */ #define SP_HDMI_US_TIMER_CTRL_REG … #define SP_MS_TIMER_MARGIN_10_8_MASK … /* * TMDS Control */ /* TMDS Control Registers */ #define SP_TMDS_CTRL_BASE … /* Bits for TMDS Control Register 7 */ #define SP_PD_RT … /* * Video Control */ /* Video Status Register */ #define SP_VIDEO_STATUS_REG … #define SP_COLOR_DEPTH_MASK … #define SP_COLOR_DEPTH_SHIFT … #define SP_COLOR_DEPTH_MODE_LEGACY … #define SP_COLOR_DEPTH_MODE_24BIT … #define SP_COLOR_DEPTH_MODE_30BIT … #define SP_COLOR_DEPTH_MODE_36BIT … #define SP_COLOR_DEPTH_MODE_48BIT … /* Video Data Range Control Register */ #define SP_VID_DATA_RANGE_CTRL_REG … #define SP_R2Y_INPUT_LIMIT … /* Pixel Clock High Resolution Counter Registers */ #define SP_PCLK_HIGHRES_CNT_BASE … /* * Audio Control */ /* Number of Audio Channels Status Registers */ #define SP_AUD_CH_STATUS_REG_NUM … /* Audio IN S/PDIF Channel Status Registers */ #define SP_AUD_SPDIF_CH_STATUS_BASE … /* Audio IN S/PDIF Channel Status Register 4 */ #define SP_FS_FREQ_MASK … #define SP_FS_FREQ_44100HZ … #define SP_FS_FREQ_48000HZ … #define SP_FS_FREQ_32000HZ … #define SP_FS_FREQ_88200HZ … #define SP_FS_FREQ_96000HZ … #define SP_FS_FREQ_176400HZ … #define SP_FS_FREQ_192000HZ … /* * Micellaneous Control Block */ /* CHIP Control Register */ #define SP_CHIP_CTRL_REG … #define SP_MAN_HDMI5V_DET … #define SP_PLLLOCK_CKDT_EN … #define SP_ANALOG_CKDT_EN … #define SP_DIGITAL_CKDT_EN … /* Packet Receiving Status Register */ #define SP_PACKET_RECEIVING_STATUS_REG … #define SP_AVI_RCVD … #define SP_VSI_RCVD … /***************************************************************/ /* Register definitions for RX_P1 */ /***************************************************************/ /* HDCP BCAPS Shadow Register */ #define SP_HDCP_BCAPS_SHADOW_REG … #define SP_BCAPS_REPEATER … /* HDCP Status Register */ #define SP_RX_HDCP_STATUS_REG … #define SP_AUTH_EN … /* * InfoFrame and Control Packet Registers */ /* AVI InfoFrame packet checksum */ #define SP_AVI_INFOFRAME_CHECKSUM … /* AVI InfoFrame Registers */ #define SP_AVI_INFOFRAME_DATA_BASE … #define SP_AVI_COLOR_F_MASK … #define SP_AVI_COLOR_F_SHIFT … /* Audio InfoFrame Registers */ #define SP_AUD_INFOFRAME_DATA_BASE … #define SP_AUD_INFOFRAME_LAYOUT_MASK … /* MPEG/HDMI Vendor Specific InfoFrame Packet type code */ #define SP_MPEG_VS_INFOFRAME_TYPE_REG … /* MPEG/HDMI Vendor Specific InfoFrame Packet length */ #define SP_MPEG_VS_INFOFRAME_LEN_REG … /* MPEG/HDMI Vendor Specific InfoFrame Packet version number */ #define SP_MPEG_VS_INFOFRAME_VER_REG … /* MPEG/HDMI Vendor Specific InfoFrame Packet content */ #define SP_MPEG_VS_INFOFRAME_DATA_BASE … /* General Control Packet Register */ #define SP_GENERAL_CTRL_PACKET_REG … #define SP_CLEAR_AVMUTE … #define SP_SET_AVMUTE … /***************************************************************/ /* Register definitions for TX_P1 */ /***************************************************************/ /* DP TX Link Training Control Register */ #define SP_DP_TX_LT_CTRL0_REG … /* PD 1.2 Lint Training 80bit Pattern Register */ #define SP_DP_LT_80BIT_PATTERN0_REG … #define SP_DP_LT_80BIT_PATTERN_REG_NUM … /* Audio Interface Control Register 0 */ #define SP_AUD_INTERFACE_CTRL0_REG … #define SP_AUD_INTERFACE_DISABLE … /* Audio Interface Control Register 2 */ #define SP_AUD_INTERFACE_CTRL2_REG … #define SP_M_AUD_ADJUST_ST … /* Audio Interface Control Register 3 */ #define SP_AUD_INTERFACE_CTRL3_REG … /* Audio Interface Control Register 4 */ #define SP_AUD_INTERFACE_CTRL4_REG … /* Audio Interface Control Register 5 */ #define SP_AUD_INTERFACE_CTRL5_REG … /* Audio Interface Control Register 6 */ #define SP_AUD_INTERFACE_CTRL6_REG … /* Firmware Version Register */ #define SP_FW_VER_REG … #endif
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