linux/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright: 2017 Cadence Design Systems, Inc.
 *
 * Author: Boris Brezillon <[email protected]>
 */

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_probe_helper.h>
#include <video/mipi_display.h>

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>

#include <linux/phy/phy-mipi-dphy.h>

#include "cdns-dsi-core.h"
#ifdef CONFIG_DRM_CDNS_DSI_J721E
#include "cdns-dsi-j721e.h"
#endif

#define IP_CONF
#define SP_HS_FIFO_DEPTH(x)
#define SP_LP_FIFO_DEPTH(x)
#define VRS_FIFO_DEPTH(x)
#define DIRCMD_FIFO_DEPTH(x)
#define SDI_IFACE_32
#define INTERNAL_DATAPATH_32
#define INTERNAL_DATAPATH_16
#define INTERNAL_DATAPATH_8
#define INTERNAL_DATAPATH_SIZE
#define NUM_IFACE(x)
#define MAX_LANE_NB(x)
#define RX_FIFO_DEPTH(x)

#define MCTL_MAIN_DATA_CTL
#define TE_MIPI_POLLING_EN
#define TE_HW_POLLING_EN
#define DISP_EOT_GEN
#define HOST_EOT_GEN
#define DISP_GEN_CHECKSUM
#define DISP_GEN_ECC
#define BTA_EN
#define READ_EN
#define REG_TE_EN
#define IF_TE_EN(x)
#define TVG_SEL
#define VID_EN
#define IF_VID_SELECT(x)
#define IF_VID_SELECT_MASK
#define IF_VID_MODE
#define LINK_EN

#define MCTL_MAIN_PHY_CTL
#define HS_INVERT_DAT(x)
#define SWAP_PINS_DAT(x)
#define HS_INVERT_CLK
#define SWAP_PINS_CLK
#define HS_SKEWCAL_EN
#define WAIT_BURST_TIME(x)
#define DATA_ULPM_EN(x)
#define CLK_ULPM_EN
#define CLK_CONTINUOUS
#define DATA_LANE_EN(x)

#define MCTL_MAIN_EN
#define DATA_FORCE_STOP
#define CLK_FORCE_STOP
#define IF_EN(x)
#define DATA_LANE_ULPM_REQ(l)
#define CLK_LANE_ULPM_REQ
#define DATA_LANE_START(x)
#define CLK_LANE_EN
#define PLL_START

#define MCTL_DPHY_CFG0
#define DPHY_C_RSTB
#define DPHY_D_RSTB(x)
#define DPHY_PLL_PDN
#define DPHY_CMN_PDN
#define DPHY_C_PDN
#define DPHY_D_PDN(x)
#define DPHY_ALL_D_PDN
#define DPHY_PLL_PSO
#define DPHY_CMN_PSO

#define MCTL_DPHY_TIMEOUT1
#define HSTX_TIMEOUT(x)
#define HSTX_TIMEOUT_MAX
#define CLK_DIV(x)
#define CLK_DIV_MAX

#define MCTL_DPHY_TIMEOUT2
#define LPRX_TIMEOUT(x)

#define MCTL_ULPOUT_TIME
#define DATA_LANE_ULPOUT_TIME(x)
#define CLK_LANE_ULPOUT_TIME(x)

#define MCTL_3DVIDEO_CTL
#define VID_VSYNC_3D_EN
#define VID_VSYNC_3D_LR
#define VID_VSYNC_3D_SECOND_EN
#define VID_VSYNC_3DFORMAT_LINE
#define VID_VSYNC_3DFORMAT_FRAME
#define VID_VSYNC_3DFORMAT_PIXEL
#define VID_VSYNC_3DMODE_OFF
#define VID_VSYNC_3DMODE_PORTRAIT
#define VID_VSYNC_3DMODE_LANDSCAPE

#define MCTL_MAIN_STS
#define MCTL_MAIN_STS_CTL
#define MCTL_MAIN_STS_CLR
#define MCTL_MAIN_STS_FLAG
#define HS_SKEWCAL_DONE
#define IF_UNTERM_PKT_ERR(x)
#define LPRX_TIMEOUT_ERR
#define HSTX_TIMEOUT_ERR
#define DATA_LANE_RDY(l)
#define CLK_LANE_RDY
#define PLL_LOCKED

#define MCTL_DPHY_ERR
#define MCTL_DPHY_ERR_CTL1
#define MCTL_DPHY_ERR_CLR
#define MCTL_DPHY_ERR_FLAG
#define ERR_CONT_LP(x, l)
#define ERR_CONTROL(l)
#define ERR_SYNESC(l)
#define ERR_ESC(l)

#define MCTL_DPHY_ERR_CTL2
#define ERR_CONT_LP_EDGE(x, l)
#define ERR_CONTROL_EDGE(l)
#define ERR_SYN_ESC_EDGE(l)
#define ERR_ESC_EDGE(l)

#define MCTL_LANE_STS
#define PPI_C_TX_READY_HS
#define DPHY_PLL_LOCK
#define PPI_D_RX_ULPS_ESC(x)
#define LANE_STATE_START
#define LANE_STATE_IDLE
#define LANE_STATE_WRITE
#define LANE_STATE_ULPM
#define LANE_STATE_READ
#define DATA_LANE_STATE(l, val)
#define CLK_LANE_STATE_HS
#define CLK_LANE_STATE(val)

#define DSC_MODE_CTL
#define DSC_MODE_EN

#define DSC_CMD_SEND
#define DSC_SEND_PPS
#define DSC_EXECUTE_QUEUE

#define DSC_PPS_WRDAT

#define DSC_MODE_STS
#define DSC_PPS_DONE
#define DSC_EXEC_DONE

#define CMD_MODE_CTL
#define IF_LP_EN(x)
#define IF_VCHAN_ID(x, c)

#define CMD_MODE_CTL2
#define TE_TIMEOUT(x)
#define FILL_VALUE(x)
#define ARB_IF_WITH_HIGHEST_PRIORITY(x)
#define ARB_ROUND_ROBIN_MODE

#define CMD_MODE_STS
#define CMD_MODE_STS_CTL
#define CMD_MODE_STS_CLR
#define CMD_MODE_STS_FLAG
#define ERR_IF_UNDERRUN(x)
#define ERR_UNWANTED_READ
#define ERR_TE_MISS
#define ERR_NO_TE
#define CSM_RUNNING

#define DIRECT_CMD_SEND

#define DIRECT_CMD_MAIN_SETTINGS
#define TRIGGER_VAL(x)
#define CMD_LP_EN
#define CMD_SIZE(x)
#define CMD_VCHAN_ID(x)
#define CMD_DATATYPE(x)
#define CMD_LONG
#define WRITE_CMD
#define READ_CMD
#define TE_REQ
#define TRIGGER_REQ
#define BTA_REQ

#define DIRECT_CMD_STS
#define DIRECT_CMD_STS_CTL
#define DIRECT_CMD_STS_CLR
#define DIRECT_CMD_STS_FLAG
#define RCVD_ACK_VAL(val)
#define RCVD_TRIGGER_VAL(val)
#define READ_COMPLETED_WITH_ERR
#define BTA_FINISHED
#define BTA_COMPLETED
#define TE_RCVD
#define TRIGGER_RCVD
#define ACK_WITH_ERR_RCVD
#define ACK_RCVD
#define READ_COMPLETED
#define TRIGGER_COMPLETED
#define WRITE_COMPLETED
#define SENDING_CMD

#define DIRECT_CMD_STOP_READ

#define DIRECT_CMD_WRDATA

#define DIRECT_CMD_FIFO_RST

#define DIRECT_CMD_RDDATA

#define DIRECT_CMD_RD_PROPS
#define RD_DCS
#define RD_VCHAN_ID(val)
#define RD_SIZE(val)

#define DIRECT_CMD_RD_STS
#define DIRECT_CMD_RD_STS_CTL
#define DIRECT_CMD_RD_STS_CLR
#define DIRECT_CMD_RD_STS_FLAG
#define ERR_EOT_WITH_ERR
#define ERR_MISSING_EOT
#define ERR_WRONG_LENGTH
#define ERR_OVERSIZE
#define ERR_RECEIVE
#define ERR_UNDECODABLE
#define ERR_CHECKSUM
#define ERR_UNCORRECTABLE
#define ERR_FIXED

#define VID_MAIN_CTL
#define VID_IGNORE_MISS_VSYNC
#define VID_FIELD_SW
#define VID_INTERLACED_EN
#define RECOVERY_MODE(x)
#define RECOVERY_MODE_NEXT_HSYNC
#define RECOVERY_MODE_NEXT_STOP_POINT
#define RECOVERY_MODE_NEXT_VSYNC
#define REG_BLKEOL_MODE(x)
#define REG_BLKLINE_MODE(x)
#define REG_BLK_MODE_NULL_PKT
#define REG_BLK_MODE_BLANKING_PKT
#define REG_BLK_MODE_LP
#define SYNC_PULSE_HORIZONTAL
#define SYNC_PULSE_ACTIVE
#define BURST_MODE
#define VID_PIXEL_MODE_MASK
#define VID_PIXEL_MODE_RGB565
#define VID_PIXEL_MODE_RGB666_PACKED
#define VID_PIXEL_MODE_RGB666
#define VID_PIXEL_MODE_RGB888
#define VID_PIXEL_MODE_RGB101010
#define VID_PIXEL_MODE_RGB121212
#define VID_PIXEL_MODE_YUV420
#define VID_PIXEL_MODE_YUV422_PACKED
#define VID_PIXEL_MODE_YUV422
#define VID_PIXEL_MODE_YUV422_24B
#define VID_PIXEL_MODE_DSC_COMP
#define VID_DATATYPE(x)
#define VID_VIRTCHAN_ID(iface, x)
#define STOP_MODE(x)
#define START_MODE(x)

#define VID_VSIZE1
#define VFP_LEN(x)
#define VBP_LEN(x)
#define VSA_LEN(x)

#define VID_VSIZE2
#define VACT_LEN(x)

#define VID_HSIZE1
#define HBP_LEN(x)
#define HSA_LEN(x)

#define VID_HSIZE2
#define HFP_LEN(x)
#define HACT_LEN(x)

#define VID_BLKSIZE1
#define BLK_EOL_PKT_LEN(x)
#define BLK_LINE_EVENT_PKT_LEN(x)

#define VID_BLKSIZE2
#define BLK_LINE_PULSE_PKT_LEN(x)

#define VID_PKT_TIME
#define BLK_EOL_DURATION(x)

#define VID_DPHY_TIME
#define REG_WAKEUP_TIME(x)
#define REG_LINE_DURATION(x)

#define VID_ERR_COLOR1
#define COL_GREEN(x)
#define COL_RED(x)

#define VID_ERR_COLOR2
#define PAD_VAL(x)
#define COL_BLUE(x)

#define VID_VPOS
#define LINE_VAL(val)
#define LINE_POS(val)

#define VID_HPOS
#define HORIZ_VAL(val)
#define HORIZ_POS(val)

#define VID_MODE_STS
#define VID_MODE_STS_CTL
#define VID_MODE_STS_CLR
#define VID_MODE_STS_FLAG
#define VSG_RECOVERY
#define ERR_VRS_WRONG_LEN
#define ERR_LONG_READ
#define ERR_LINE_WRITE
#define ERR_BURST_WRITE
#define ERR_SMALL_HEIGHT
#define ERR_SMALL_LEN
#define ERR_MISSING_VSYNC
#define ERR_MISSING_HSYNC
#define ERR_MISSING_DATA
#define VSG_RUNNING

#define VID_VCA_SETTING1
#define BURST_LP
#define MAX_BURST_LIMIT(x)

#define VID_VCA_SETTING2
#define MAX_LINE_LIMIT(x)
#define EXACT_BURST_LIMIT(x)

#define TVG_CTL
#define TVG_STRIPE_SIZE(x)
#define TVG_MODE_MASK
#define TVG_MODE_SINGLE_COLOR
#define TVG_MODE_VSTRIPES
#define TVG_MODE_HSTRIPES
#define TVG_STOPMODE_MASK
#define TVG_STOPMODE_EOF
#define TVG_STOPMODE_EOL
#define TVG_STOPMODE_NOW
#define TVG_RUN

#define TVG_IMG_SIZE
#define TVG_NBLINES(x)
#define TVG_LINE_SIZE(x)

#define TVG_COLOR1
#define TVG_COL1_GREEN(x)
#define TVG_COL1_RED(x)

#define TVG_COLOR1_BIS
#define TVG_COL1_BLUE(x)

#define TVG_COLOR2
#define TVG_COL2_GREEN(x)
#define TVG_COL2_RED(x)

#define TVG_COLOR2_BIS
#define TVG_COL2_BLUE(x)

#define TVG_STS
#define TVG_STS_CTL
#define TVG_STS_CLR
#define TVG_STS_FLAG
#define TVG_STS_RUNNING

#define STS_CTL_EDGE(e)

#define DPHY_LANES_MAP
#define DAT_REMAP_CFG(b, l)

#define DPI_IRQ_EN
#define DPI_IRQ_CLR
#define DPI_IRQ_STS
#define PIXEL_BUF_OVERFLOW

#define DPI_CFG
#define DPI_CFG_FIFO_DEPTH(x)
#define DPI_CFG_FIFO_LEVEL(x)

#define TEST_GENERIC
#define TEST_STATUS(x)
#define TEST_CTRL(x)

#define ID_REG
#define REV_VENDOR_ID(x)
#define REV_PRODUCT_ID(x)
#define REV_HW(x)
#define REV_MAJOR(x)
#define REV_MINOR(x)

#define DSI_OUTPUT_PORT
#define DSI_INPUT_PORT(inputid)

#define DSI_HBP_FRAME_OVERHEAD
#define DSI_HSA_FRAME_OVERHEAD
#define DSI_HFP_FRAME_OVERHEAD
#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD
#define DSI_BLANKING_FRAME_OVERHEAD
#define DSI_NULL_FRAME_OVERHEAD
#define DSI_EOT_PKT_SIZE

static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{}

static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)
{}

static inline struct cdns_dsi_input *
bridge_to_cdns_dsi_input(struct drm_bridge *bridge)
{}

static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,
				    bool mode_valid_check)
{}

static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,
				      unsigned int dpi_bpp,
				      unsigned int dsi_pkt_overhead)
{}

static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
			     const struct drm_display_mode *mode,
			     struct cdns_dsi_cfg *dsi_cfg,
			     bool mode_valid_check)
{}

static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
			      struct cdns_dsi_cfg *dsi_cfg,
			      struct phy_configure_opts_mipi_dphy *phy_cfg,
			      const struct drm_display_mode *mode,
			      bool mode_valid_check)
{}

static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
			       const struct drm_display_mode *mode,
			       struct cdns_dsi_cfg *dsi_cfg,
			       bool mode_valid_check)
{}

static int cdns_dsi_bridge_attach(struct drm_bridge *bridge,
				  enum drm_bridge_attach_flags flags)
{}

static enum drm_mode_status
cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,
			   const struct drm_display_info *info,
			   const struct drm_display_mode *mode)
{}

static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
{}

static void cdns_dsi_bridge_post_disable(struct drm_bridge *bridge)
{}

static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
{}

static void cdns_dsi_init_link(struct cdns_dsi *dsi)
{}

static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
{}

static void cdns_dsi_bridge_pre_enable(struct drm_bridge *bridge)
{}

static const struct drm_bridge_funcs cdns_dsi_bridge_funcs =;

static int cdns_dsi_attach(struct mipi_dsi_host *host,
			   struct mipi_dsi_device *dev)
{}

static int cdns_dsi_detach(struct mipi_dsi_host *host,
			   struct mipi_dsi_device *dev)
{}

static irqreturn_t cdns_dsi_interrupt(int irq, void *data)
{}

static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
				 const struct mipi_dsi_msg *msg)
{}

static const struct mipi_dsi_host_ops cdns_dsi_ops =;

static int __maybe_unused cdns_dsi_resume(struct device *dev)
{}

static int __maybe_unused cdns_dsi_suspend(struct device *dev)
{}

static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume,
			    NULL);

static int cdns_dsi_drm_probe(struct platform_device *pdev)
{}

static void cdns_dsi_drm_remove(struct platform_device *pdev)
{}

static const struct of_device_id cdns_dsi_of_match[] =;
MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);

static struct platform_driver cdns_dsi_platform_driver =;
module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_ALIAS();