linux/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Cadence MHDP8546 DP bridge driver.
 *
 * Copyright (C) 2020 Cadence Design Systems, Inc.
 *
 * Author: Quentin Schulz <[email protected]>
 *         Swapnil Jakhade <[email protected]>
 */

#ifndef CDNS_MHDP8546_CORE_H
#define CDNS_MHDP8546_CORE_H

#include <linux/bits.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>

#include <drm/display/drm_dp_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_connector.h>

struct clk;
struct device;
struct phy;

/* Register offsets */
#define CDNS_APB_CTRL
#define CDNS_CPU_STALL

#define CDNS_MAILBOX_FULL
#define CDNS_MAILBOX_EMPTY
#define CDNS_MAILBOX_TX_DATA
#define CDNS_MAILBOX_RX_DATA
#define CDNS_KEEP_ALIVE
#define CDNS_KEEP_ALIVE_MASK

#define CDNS_VER_L
#define CDNS_VER_H
#define CDNS_LIB_L_ADDR
#define CDNS_LIB_H_ADDR

#define CDNS_MB_INT_MASK
#define CDNS_MB_INT_STATUS

#define CDNS_SW_CLK_L
#define CDNS_SW_CLK_H

#define CDNS_SW_EVENT0
#define CDNS_DPTX_HPD
#define CDNS_HDCP_TX_STATUS
#define CDNS_HDCP2_TX_IS_KM_STORED
#define CDNS_HDCP2_TX_STORE_KM
#define CDNS_HDCP_TX_IS_RCVR_ID_VALID

#define CDNS_SW_EVENT1
#define CDNS_SW_EVENT2
#define CDNS_SW_EVENT3

#define CDNS_APB_INT_MASK
#define CDNS_APB_INT_MASK_MAILBOX_INT
#define CDNS_APB_INT_MASK_SW_EVENT_INT

#define CDNS_APB_INT_STATUS

#define CDNS_DPTX_CAR
#define CDNS_VIF_CLK_EN
#define CDNS_VIF_CLK_RSTN

#define CDNS_SOURCE_VIDEO_IF(s)
#define CDNS_BND_HSYNC2VSYNC(s)
#define CDNS_IP_DTCT_WIN
#define CDNS_IP_DET_INTERLACE_FORMAT
#define CDNS_IP_BYPASS_V_INTERFACE

#define CDNS_HSYNC2VSYNC_POL_CTRL(s)
#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW
#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW

#define CDNS_DPTX_PHY_CONFIG
#define CDNS_PHY_TRAINING_EN
#define CDNS_PHY_TRAINING_TYPE(x)
#define CDNS_PHY_SCRAMBLER_BYPASS
#define CDNS_PHY_ENCODER_BYPASS
#define CDNS_PHY_SKEW_BYPASS
#define CDNS_PHY_TRAINING_AUTO
#define CDNS_PHY_LANE0_SKEW(x)
#define CDNS_PHY_LANE1_SKEW(x)
#define CDNS_PHY_LANE2_SKEW(x)
#define CDNS_PHY_LANE3_SKEW(x)
#define CDNS_PHY_COMMON_CONFIG
#define CDNS_PHY_10BIT_EN

#define CDNS_DP_FRAMER_GLOBAL_CONFIG
#define CDNS_DP_NUM_LANES(x)
#define CDNS_DP_MST_EN
#define CDNS_DP_FRAMER_EN
#define CDNS_DP_RATE_GOVERNOR_EN
#define CDNS_DP_NO_VIDEO_MODE
#define CDNS_DP_DISABLE_PHY_RST
#define CDNS_DP_WR_FAILING_EDGE_VSYNC

#define CDNS_DP_FRAMER_TU
#define CDNS_DP_FRAMER_TU_SIZE(x)
#define CDNS_DP_FRAMER_TU_VS(x)
#define CDNS_DP_FRAMER_TU_CNT_RST_EN

#define CDNS_DP_MTPH_CONTROL
#define CDNS_DP_MTPH_ECF_EN
#define CDNS_DP_MTPH_ACT_EN
#define CDNS_DP_MTPH_LVP_EN

#define CDNS_DP_MTPH_STATUS
#define CDNS_DP_MTPH_ACT_STATUS

#define CDNS_DP_LANE_EN
#define CDNS_DP_LANE_EN_LANES(x)

#define CDNS_DP_ENHNCD

#define CDNS_DPTX_STREAM(s)
#define CDNS_DP_MSA_HORIZONTAL_0(s)
#define CDNS_DP_MSAH0_H_TOTAL(x)
#define CDNS_DP_MSAH0_HSYNC_START(x)

#define CDNS_DP_MSA_HORIZONTAL_1(s)
#define CDNS_DP_MSAH1_HSYNC_WIDTH(x)
#define CDNS_DP_MSAH1_HSYNC_POL_LOW
#define CDNS_DP_MSAH1_HDISP_WIDTH(x)

#define CDNS_DP_MSA_VERTICAL_0(s)
#define CDNS_DP_MSAV0_V_TOTAL(x)
#define CDNS_DP_MSAV0_VSYNC_START(x)

#define CDNS_DP_MSA_VERTICAL_1(s)
#define CDNS_DP_MSAV1_VSYNC_WIDTH(x)
#define CDNS_DP_MSAV1_VSYNC_POL_LOW
#define CDNS_DP_MSAV1_VDISP_WIDTH(x)

#define CDNS_DP_MSA_MISC(s)
#define CDNS_DP_STREAM_CONFIG(s)
#define CDNS_DP_STREAM_CONFIG_2(s)
#define CDNS_DP_SC2_TU_VS_DIFF(x)

#define CDNS_DP_HORIZONTAL(s)
#define CDNS_DP_H_HSYNC_WIDTH(x)
#define CDNS_DP_H_H_TOTAL(x)

#define CDNS_DP_VERTICAL_0(s)
#define CDNS_DP_V0_VHEIGHT(x)
#define CDNS_DP_V0_VSTART(x)

#define CDNS_DP_VERTICAL_1(s)
#define CDNS_DP_V1_VTOTAL(x)
#define CDNS_DP_V1_VTOTAL_EVEN

#define CDNS_DP_MST_SLOT_ALLOCATE(s)
#define CDNS_DP_S_ALLOC_START_SLOT(x)
#define CDNS_DP_S_ALLOC_END_SLOT(x)

#define CDNS_DP_RATE_GOVERNING(s)
#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x)
#define CDNS_DP_RG_TARG_AV_SLOTS_X(x)
#define CDNS_DP_RG_ENABLE

#define CDNS_DP_FRAMER_PXL_REPR(s)
#define CDNS_DP_FRAMER_6_BPC
#define CDNS_DP_FRAMER_8_BPC
#define CDNS_DP_FRAMER_10_BPC
#define CDNS_DP_FRAMER_12_BPC
#define CDNS_DP_FRAMER_16_BPC
#define CDNS_DP_FRAMER_PXL_FORMAT
#define CDNS_DP_FRAMER_RGB
#define CDNS_DP_FRAMER_YCBCR444
#define CDNS_DP_FRAMER_YCBCR422
#define CDNS_DP_FRAMER_YCBCR420
#define CDNS_DP_FRAMER_Y_ONLY

#define CDNS_DP_FRAMER_SP(s)
#define CDNS_DP_FRAMER_VSYNC_POL_LOW
#define CDNS_DP_FRAMER_HSYNC_POL_LOW
#define CDNS_DP_FRAMER_INTERLACE

#define CDNS_DP_LINE_THRESH(s)
#define CDNS_DP_ACTIVE_LINE_THRESH(x)

#define CDNS_DP_VB_ID(s)
#define CDNS_DP_VB_ID_INTERLACED
#define CDNS_DP_VB_ID_COMPRESSED

#define CDNS_DP_FRONT_BACK_PORCH(s)
#define CDNS_DP_BACK_PORCH(x)
#define CDNS_DP_FRONT_PORCH(x)

#define CDNS_DP_BYTE_COUNT(s)
#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT

/* mailbox */
#define MAILBOX_RETRY_US
#define MAILBOX_TIMEOUT_US

#define MB_OPCODE_ID
#define MB_MODULE_ID
#define MB_SIZE_MSB_ID
#define MB_SIZE_LSB_ID
#define MB_DATA_ID

#define MB_MODULE_ID_DP_TX
#define MB_MODULE_ID_HDCP_TX
#define MB_MODULE_ID_HDCP_RX
#define MB_MODULE_ID_HDCP_GENERAL
#define MB_MODULE_ID_GENERAL

/* firmware and opcodes */
#define FW_NAME
#define CDNS_MHDP_IMEM

#define GENERAL_MAIN_CONTROL
#define GENERAL_TEST_ECHO
#define GENERAL_BUS_SETTINGS
#define GENERAL_TEST_ACCESS
#define GENERAL_REGISTER_READ

#define DPTX_SET_POWER_MNG
#define DPTX_GET_EDID
#define DPTX_READ_DPCD
#define DPTX_WRITE_DPCD
#define DPTX_ENABLE_EVENT
#define DPTX_WRITE_REGISTER
#define DPTX_READ_REGISTER
#define DPTX_WRITE_FIELD
#define DPTX_READ_EVENT
#define DPTX_GET_LAST_AUX_STAUS
#define DPTX_HPD_STATE
#define DPTX_ADJUST_LT

#define FW_STANDBY
#define FW_ACTIVE

/* HPD */
#define DPTX_READ_EVENT_HPD_TO_HIGH
#define DPTX_READ_EVENT_HPD_TO_LOW
#define DPTX_READ_EVENT_HPD_PULSE
#define DPTX_READ_EVENT_HPD_STATE

/* general */
#define CDNS_DP_TRAINING_PATTERN_4

#define CDNS_KEEP_ALIVE_TIMEOUT

#define CDNS_VOLT_SWING(x)
#define CDNS_FORCE_VOLT_SWING

#define CDNS_PRE_EMPHASIS(x)
#define CDNS_FORCE_PRE_EMPHASIS

#define CDNS_SUPPORT_TPS(x)

#define CDNS_FAST_LINK_TRAINING

#define CDNS_LANE_MAPPING_TYPE_C_LANE_0(x)
#define CDNS_LANE_MAPPING_TYPE_C_LANE_1(x)
#define CDNS_LANE_MAPPING_TYPE_C_LANE_2(x)
#define CDNS_LANE_MAPPING_TYPE_C_LANE_3(x)
#define CDNS_LANE_MAPPING_NORMAL
#define CDNS_LANE_MAPPING_FLIPPED

#define CDNS_DP_MAX_NUM_LANES
#define CDNS_DP_TEST_VSC_SDP
#define CDNS_DP_TEST_COLOR_FORMAT_RAW_Y_ONLY

#define CDNS_MHDP_MAX_STREAMS

#define DP_LINK_CAP_ENHANCED_FRAMING

struct cdns_mhdp_link {};

struct cdns_mhdp_host {};

struct cdns_mhdp_sink {};

struct cdns_mhdp_display_fmt {};

/*
 * These enums present MHDP hw initialization state
 * Legal state transitions are:
 * MHDP_HW_READY <-> MHDP_HW_STOPPED
 */
enum mhdp_hw_state {};

struct cdns_mhdp_device;

struct mhdp_platform_ops {};

struct cdns_mhdp_bridge_state {};

struct cdns_mhdp_platform_info {};

#define to_cdns_mhdp_bridge_state(s)

struct cdns_mhdp_hdcp {};

struct cdns_mhdp_device {};

#define connector_to_mhdp(x)
#define bridge_to_mhdp(x)

u32 cdns_mhdp_wait_for_sw_event(struct cdns_mhdp_device *mhdp, uint32_t event);

#endif