linux/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

// SPDX-License-Identifier: GPL-2.0+

/*
 * Copyright 2020 NXP
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <drm/drm_atomic_state_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_print.h>

#define PC_CTRL_REG …
#define PC_COMBINE_ENABLE …
#define PC_DISP_BYPASS(n) …
#define PC_DISP_HSYNC_POLARITY(n) …
#define PC_DISP_HSYNC_POLARITY_POS(n) …
#define PC_DISP_VSYNC_POLARITY(n) …
#define PC_DISP_VSYNC_POLARITY_POS(n) …
#define PC_DISP_DVALID_POLARITY(n) …
#define PC_DISP_DVALID_POLARITY_POS(n) …
#define PC_VSYNC_MASK_ENABLE …
#define PC_SKIP_MODE …
#define PC_SKIP_NUMBER_MASK …
#define PC_SKIP_NUMBER(n) …
#define PC_DISP0_PIX_DATA_FORMAT_MASK …
#define PC_DISP0_PIX_DATA_FORMAT(fmt) …
#define PC_DISP1_PIX_DATA_FORMAT_MASK …
#define PC_DISP1_PIX_DATA_FORMAT(fmt) …

#define PC_SW_RESET_REG …
#define PC_SW_RESET_N …
#define PC_DISP_SW_RESET_N(n) …
#define PC_FULL_RESET_N …

#define PC_REG_SET …
#define PC_REG_CLR …

#define DRIVER_NAME …

enum imx8qxp_pc_pix_data_format { … };

struct imx8qxp_pc_channel { … };

struct imx8qxp_pc { … };

static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset)
{ … }

static inline void
imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
{ … }

static inline void
imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
{ … }

static inline void
imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
{ … }

static enum drm_mode_status
imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge,
			     const struct drm_display_info *info,
			     const struct drm_display_mode *mode)
{ … }

static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge,
				    enum drm_bridge_attach_flags flags)
{ … }

static void
imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge,
			   const struct drm_display_mode *mode,
			   const struct drm_display_mode *adjusted_mode)
{ … }

static void
imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge,
				 struct drm_bridge_state *old_bridge_state)
{ … }

static const u32 imx8qxp_pc_bus_output_fmts[] = …;

static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt)
{ … }

static u32 *
imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
					    struct drm_bridge_state *bridge_state,
					    struct drm_crtc_state *crtc_state,
					    struct drm_connector_state *conn_state,
					    u32 output_fmt,
					    unsigned int *num_input_fmts)
{ … }

static u32 *
imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
					     struct drm_bridge_state *bridge_state,
					     struct drm_crtc_state *crtc_state,
					     struct drm_connector_state *conn_state,
					     unsigned int *num_output_fmts)
{ … }

static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = …;

static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
{ … }

static void imx8qxp_pc_bridge_remove(struct platform_device *pdev)
{ … }

static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev)
{ … }

static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev)
{ … }

static const struct dev_pm_ops imx8qxp_pc_pm_ops = …;

static const struct of_device_id imx8qxp_pc_dt_ids[] = …;
MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids);

static struct platform_driver imx8qxp_pc_bridge_driver = …;
module_platform_driver(…) …;

MODULE_DESCRIPTION(…) …;
MODULE_AUTHOR(…) …;
MODULE_LICENSE(…) …;
MODULE_ALIAS(…) …;