// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2022,2023 NXP */ #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/math.h> #include <linux/media-bus-format.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/phy/phy-mipi-dphy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <drm/bridge/dw_mipi_dsi.h> #include <drm/drm_bridge.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_modes.h> /* DPHY PLL configuration registers */ #define DSI_REG … #define CFGCLKFREQRANGE_MASK … #define CFGCLKFREQRANGE(x) … #define CLKSEL_MASK … #define CLKSEL_STOP … #define CLKSEL_GEN … #define CLKSEL_EXT … #define HSFREQRANGE_MASK … #define HSFREQRANGE(x) … #define UPDATE_PLL … #define SHADOW_CLR … #define CLK_EXT … #define DSI_WRITE_REG0 … #define M_MASK … #define M(x) … #define N_MASK … #define N(x) … #define VCO_CTRL_MASK … #define VCO_CTRL(x) … #define PROP_CTRL_MASK … #define PROP_CTRL(x) … #define INT_CTRL_MASK … #define INT_CTRL(x) … #define DSI_WRITE_REG1 … #define GMP_CTRL_MASK … #define GMP_CTRL(x) … #define CPBIAS_CTRL_MASK … #define CPBIAS_CTRL(x) … #define PLL_SHADOW_CTRL … /* display mux control register */ #define DISPLAY_MUX … #define MIPI_DSI_RGB666_MAP_CFG … #define RGB666_CONFIG1 … #define RGB666_CONFIG2 … #define MIPI_DSI_RGB565_MAP_CFG … #define RGB565_CONFIG1 … #define RGB565_CONFIG2 … #define RGB565_CONFIG3 … #define LCDIF_CROSS_LINE_PATTERN … #define RGB888_TO_RGB888 … #define RGB888_TO_RGB666 … #define RGB565_TO_RGB565 … #define MHZ(x) … #define REF_CLK_RATE_MAX … #define REF_CLK_RATE_MIN … #define FOUT_MAX … #define FOUT_MIN … #define FVCO_DIV_FACTOR … #define MBPS(x) … #define DATA_RATE_MAX_SPEED … #define DATA_RATE_MIN_SPEED … #define M_MAX … #define M_MIN … #define N_MAX … #define N_MIN … struct imx93_dsi { … }; struct dphy_pll_cfg { … }; struct dphy_pll_vco_prop { … }; struct dphy_pll_hsfreqrange { … }; /* DPHY Databook Table 3-13 Charge-pump Programmability */ static const struct dphy_pll_vco_prop vco_prop_map[] = …; /* DPHY Databook Table 5-7 Frequency Ranges and Defaults */ static const struct dphy_pll_hsfreqrange hsfreqrange_map[] = …; static void dphy_pll_write(struct imx93_dsi *dsi, unsigned int reg, u32 value) { … } static inline unsigned long data_rate_to_fout(unsigned long data_rate) { … } static int dphy_pll_get_configure_from_opts(struct imx93_dsi *dsi, struct phy_configure_opts_mipi_dphy *dphy_opts, struct dphy_pll_cfg *cfg) { … } static void dphy_pll_clear_shadow(struct imx93_dsi *dsi) { … } static unsigned long dphy_pll_get_cfgclkrange(struct imx93_dsi *dsi) { … } static u8 dphy_pll_get_hsfreqrange(struct phy_configure_opts_mipi_dphy *dphy_opts) { … } static u8 dphy_pll_get_vco(struct phy_configure_opts_mipi_dphy *dphy_opts) { … } static u8 dphy_pll_get_prop(struct phy_configure_opts_mipi_dphy *dphy_opts) { … } static int dphy_pll_update(struct imx93_dsi *dsi) { … } static int dphy_pll_configure(struct imx93_dsi *dsi, union phy_configure_opts *opts) { … } static void dphy_pll_clear_reg(struct imx93_dsi *dsi) { … } static int dphy_pll_init(struct imx93_dsi *dsi) { … } static void dphy_pll_uninit(struct imx93_dsi *dsi) { … } static void dphy_pll_power_off(struct imx93_dsi *dsi) { … } static int imx93_dsi_get_phy_configure_opts(struct imx93_dsi *dsi, const struct drm_display_mode *mode, union phy_configure_opts *phy_cfg, u32 lanes, u32 format) { … } static enum drm_mode_status imx93_dsi_validate_mode(struct imx93_dsi *dsi, const struct drm_display_mode *mode) { … } static enum drm_mode_status imx93_dsi_validate_phy(struct imx93_dsi *dsi, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format) { … } static enum drm_mode_status imx93_dsi_mode_valid(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format) { … } static bool imx93_dsi_mode_fixup(void *priv_data, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { … } static u32 *imx93_dsi_get_input_bus_fmts(void *priv_data, struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts) { … } static int imx93_dsi_phy_init(void *priv_data) { … } static void imx93_dsi_phy_power_off(void *priv_data) { … } static int imx93_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, unsigned int *lane_mbps) { … } /* High-Speed Transition Times */ struct hstt { … }; #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) … /* DPHY Databook Table A-4 High-Speed Transition Times */ static const struct hstt hstt_table[] = …; static int imx93_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, struct dw_mipi_dsi_dphy_timing *timing) { … } static const struct dw_mipi_dsi_phy_ops imx93_dsi_phy_ops = …; static int imx93_dsi_host_attach(void *priv_data, struct mipi_dsi_device *device) { … } static const struct dw_mipi_dsi_host_ops imx93_dsi_host_ops = …; static int imx93_dsi_probe(struct platform_device *pdev) { … } static void imx93_dsi_remove(struct platform_device *pdev) { … } static const struct of_device_id imx93_dsi_dt_ids[] = …; MODULE_DEVICE_TABLE(of, imx93_dsi_dt_ids); static struct platform_driver imx93_dsi_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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