/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2011 Freescale Semiconductor, Inc. */ #ifndef __DW_HDMI_H__ #define __DW_HDMI_H__ /* Identification Registers */ #define HDMI_DESIGN_ID … #define HDMI_REVISION_ID … #define HDMI_PRODUCT_ID0 … #define HDMI_PRODUCT_ID1 … #define HDMI_CONFIG0_ID … #define HDMI_CONFIG1_ID … #define HDMI_CONFIG2_ID … #define HDMI_CONFIG3_ID … /* Interrupt Registers */ #define HDMI_IH_FC_STAT0 … #define HDMI_IH_FC_STAT1 … #define HDMI_IH_FC_STAT2 … #define HDMI_IH_AS_STAT0 … #define HDMI_IH_PHY_STAT0 … #define HDMI_IH_I2CM_STAT0 … #define HDMI_IH_CEC_STAT0 … #define HDMI_IH_VP_STAT0 … #define HDMI_IH_I2CMPHY_STAT0 … #define HDMI_IH_AHBDMAAUD_STAT0 … #define HDMI_IH_MUTE_FC_STAT0 … #define HDMI_IH_MUTE_FC_STAT1 … #define HDMI_IH_MUTE_FC_STAT2 … #define HDMI_IH_MUTE_AS_STAT0 … #define HDMI_IH_MUTE_PHY_STAT0 … #define HDMI_IH_MUTE_I2CM_STAT0 … #define HDMI_IH_MUTE_CEC_STAT0 … #define HDMI_IH_MUTE_VP_STAT0 … #define HDMI_IH_MUTE_I2CMPHY_STAT0 … #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 … #define HDMI_IH_MUTE … /* Video Sample Registers */ #define HDMI_TX_INVID0 … #define HDMI_TX_INSTUFFING … #define HDMI_TX_GYDATA0 … #define HDMI_TX_GYDATA1 … #define HDMI_TX_RCRDATA0 … #define HDMI_TX_RCRDATA1 … #define HDMI_TX_BCBDATA0 … #define HDMI_TX_BCBDATA1 … /* Video Packetizer Registers */ #define HDMI_VP_STATUS … #define HDMI_VP_PR_CD … #define HDMI_VP_STUFF … #define HDMI_VP_REMAP … #define HDMI_VP_CONF … #define HDMI_VP_STAT … #define HDMI_VP_INT … #define HDMI_VP_MASK … #define HDMI_VP_POL … /* Frame Composer Registers */ #define HDMI_FC_INVIDCONF … #define HDMI_FC_INHACTV0 … #define HDMI_FC_INHACTV1 … #define HDMI_FC_INHBLANK0 … #define HDMI_FC_INHBLANK1 … #define HDMI_FC_INVACTV0 … #define HDMI_FC_INVACTV1 … #define HDMI_FC_INVBLANK … #define HDMI_FC_HSYNCINDELAY0 … #define HDMI_FC_HSYNCINDELAY1 … #define HDMI_FC_HSYNCINWIDTH0 … #define HDMI_FC_HSYNCINWIDTH1 … #define HDMI_FC_VSYNCINDELAY … #define HDMI_FC_VSYNCINWIDTH … #define HDMI_FC_INFREQ0 … #define HDMI_FC_INFREQ1 … #define HDMI_FC_INFREQ2 … #define HDMI_FC_CTRLDUR … #define HDMI_FC_EXCTRLDUR … #define HDMI_FC_EXCTRLSPAC … #define HDMI_FC_CH0PREAM … #define HDMI_FC_CH1PREAM … #define HDMI_FC_CH2PREAM … #define HDMI_FC_AVICONF3 … #define HDMI_FC_GCP … #define HDMI_FC_AVICONF0 … #define HDMI_FC_AVICONF1 … #define HDMI_FC_AVICONF2 … #define HDMI_FC_AVIVID … #define HDMI_FC_AVIETB0 … #define HDMI_FC_AVIETB1 … #define HDMI_FC_AVISBB0 … #define HDMI_FC_AVISBB1 … #define HDMI_FC_AVIELB0 … #define HDMI_FC_AVIELB1 … #define HDMI_FC_AVISRB0 … #define HDMI_FC_AVISRB1 … #define HDMI_FC_AUDICONF0 … #define HDMI_FC_AUDICONF1 … #define HDMI_FC_AUDICONF2 … #define HDMI_FC_AUDICONF3 … #define HDMI_FC_VSDIEEEID0 … #define HDMI_FC_VSDSIZE … #define HDMI_FC_VSDIEEEID1 … #define HDMI_FC_VSDIEEEID2 … #define HDMI_FC_VSDPAYLOAD0 … #define HDMI_FC_VSDPAYLOAD1 … #define HDMI_FC_VSDPAYLOAD2 … #define HDMI_FC_VSDPAYLOAD3 … #define HDMI_FC_VSDPAYLOAD4 … #define HDMI_FC_VSDPAYLOAD5 … #define HDMI_FC_VSDPAYLOAD6 … #define HDMI_FC_VSDPAYLOAD7 … #define HDMI_FC_VSDPAYLOAD8 … #define HDMI_FC_VSDPAYLOAD9 … #define HDMI_FC_VSDPAYLOAD10 … #define HDMI_FC_VSDPAYLOAD11 … #define HDMI_FC_VSDPAYLOAD12 … #define HDMI_FC_VSDPAYLOAD13 … #define HDMI_FC_VSDPAYLOAD14 … #define HDMI_FC_VSDPAYLOAD15 … #define HDMI_FC_VSDPAYLOAD16 … #define HDMI_FC_VSDPAYLOAD17 … #define HDMI_FC_VSDPAYLOAD18 … #define HDMI_FC_VSDPAYLOAD19 … #define HDMI_FC_VSDPAYLOAD20 … #define HDMI_FC_VSDPAYLOAD21 … #define HDMI_FC_VSDPAYLOAD22 … #define HDMI_FC_VSDPAYLOAD23 … #define HDMI_FC_SPDVENDORNAME0 … #define HDMI_FC_SPDVENDORNAME1 … #define HDMI_FC_SPDVENDORNAME2 … #define HDMI_FC_SPDVENDORNAME3 … #define HDMI_FC_SPDVENDORNAME4 … #define HDMI_FC_SPDVENDORNAME5 … #define HDMI_FC_SPDVENDORNAME6 … #define HDMI_FC_SPDVENDORNAME7 … #define HDMI_FC_SDPPRODUCTNAME0 … #define HDMI_FC_SDPPRODUCTNAME1 … #define HDMI_FC_SDPPRODUCTNAME2 … #define HDMI_FC_SDPPRODUCTNAME3 … #define HDMI_FC_SDPPRODUCTNAME4 … #define HDMI_FC_SDPPRODUCTNAME5 … #define HDMI_FC_SDPPRODUCTNAME6 … #define HDMI_FC_SDPPRODUCTNAME7 … #define HDMI_FC_SDPPRODUCTNAME8 … #define HDMI_FC_SDPPRODUCTNAME9 … #define HDMI_FC_SDPPRODUCTNAME10 … #define HDMI_FC_SDPPRODUCTNAME11 … #define HDMI_FC_SDPPRODUCTNAME12 … #define HDMI_FC_SDPPRODUCTNAME13 … #define HDMI_FC_SDPPRODUCTNAME14 … #define HDMI_FC_SPDPRODUCTNAME15 … #define HDMI_FC_SPDDEVICEINF … #define HDMI_FC_AUDSCONF … #define HDMI_FC_AUDSSTAT … #define HDMI_FC_AUDSV … #define HDMI_FC_AUDSU … #define HDMI_FC_AUDSCHNLS0 … #define HDMI_FC_AUDSCHNLS1 … #define HDMI_FC_AUDSCHNLS2 … #define HDMI_FC_AUDSCHNLS3 … #define HDMI_FC_AUDSCHNLS4 … #define HDMI_FC_AUDSCHNLS5 … #define HDMI_FC_AUDSCHNLS6 … #define HDMI_FC_AUDSCHNLS7 … #define HDMI_FC_AUDSCHNLS8 … #define HDMI_FC_DATACH0FILL … #define HDMI_FC_DATACH1FILL … #define HDMI_FC_DATACH2FILL … #define HDMI_FC_CTRLQHIGH … #define HDMI_FC_CTRLQLOW … #define HDMI_FC_ACP0 … #define HDMI_FC_ACP28 … #define HDMI_FC_ACP27 … #define HDMI_FC_ACP26 … #define HDMI_FC_ACP25 … #define HDMI_FC_ACP24 … #define HDMI_FC_ACP23 … #define HDMI_FC_ACP22 … #define HDMI_FC_ACP21 … #define HDMI_FC_ACP20 … #define HDMI_FC_ACP19 … #define HDMI_FC_ACP18 … #define HDMI_FC_ACP17 … #define HDMI_FC_ACP16 … #define HDMI_FC_ACP15 … #define HDMI_FC_ACP14 … #define HDMI_FC_ACP13 … #define HDMI_FC_ACP12 … #define HDMI_FC_ACP11 … #define HDMI_FC_ACP10 … #define HDMI_FC_ACP9 … #define HDMI_FC_ACP8 … #define HDMI_FC_ACP7 … #define HDMI_FC_ACP6 … #define HDMI_FC_ACP5 … #define HDMI_FC_ACP4 … #define HDMI_FC_ACP3 … #define HDMI_FC_ACP2 … #define HDMI_FC_ACP1 … #define HDMI_FC_ISCR1_0 … #define HDMI_FC_ISCR1_16 … #define HDMI_FC_ISCR1_15 … #define HDMI_FC_ISCR1_14 … #define HDMI_FC_ISCR1_13 … #define HDMI_FC_ISCR1_12 … #define HDMI_FC_ISCR1_11 … #define HDMI_FC_ISCR1_10 … #define HDMI_FC_ISCR1_9 … #define HDMI_FC_ISCR1_8 … #define HDMI_FC_ISCR1_7 … #define HDMI_FC_ISCR1_6 … #define HDMI_FC_ISCR1_5 … #define HDMI_FC_ISCR1_4 … #define HDMI_FC_ISCR1_3 … #define HDMI_FC_ISCR1_2 … #define HDMI_FC_ISCR1_1 … #define HDMI_FC_ISCR2_15 … #define HDMI_FC_ISCR2_14 … #define HDMI_FC_ISCR2_13 … #define HDMI_FC_ISCR2_12 … #define HDMI_FC_ISCR2_11 … #define HDMI_FC_ISCR2_10 … #define HDMI_FC_ISCR2_9 … #define HDMI_FC_ISCR2_8 … #define HDMI_FC_ISCR2_7 … #define HDMI_FC_ISCR2_6 … #define HDMI_FC_ISCR2_5 … #define HDMI_FC_ISCR2_4 … #define HDMI_FC_ISCR2_3 … #define HDMI_FC_ISCR2_2 … #define HDMI_FC_ISCR2_1 … #define HDMI_FC_ISCR2_0 … #define HDMI_FC_DATAUTO0 … #define HDMI_FC_DATAUTO1 … #define HDMI_FC_DATAUTO2 … #define HDMI_FC_DATMAN … #define HDMI_FC_DATAUTO3 … #define HDMI_FC_RDRB0 … #define HDMI_FC_RDRB1 … #define HDMI_FC_RDRB2 … #define HDMI_FC_RDRB3 … #define HDMI_FC_RDRB4 … #define HDMI_FC_RDRB5 … #define HDMI_FC_RDRB6 … #define HDMI_FC_RDRB7 … #define HDMI_FC_STAT0 … #define HDMI_FC_INT0 … #define HDMI_FC_MASK0 … #define HDMI_FC_POL0 … #define HDMI_FC_STAT1 … #define HDMI_FC_INT1 … #define HDMI_FC_MASK1 … #define HDMI_FC_POL1 … #define HDMI_FC_STAT2 … #define HDMI_FC_INT2 … #define HDMI_FC_MASK2 … #define HDMI_FC_POL2 … #define HDMI_FC_PRCONF … #define HDMI_FC_SCRAMBLER_CTRL … #define HDMI_FC_PACKET_TX_EN … #define HDMI_FC_GMD_STAT … #define HDMI_FC_GMD_EN … #define HDMI_FC_GMD_UP … #define HDMI_FC_GMD_CONF … #define HDMI_FC_GMD_HB … #define HDMI_FC_GMD_PB0 … #define HDMI_FC_GMD_PB1 … #define HDMI_FC_GMD_PB2 … #define HDMI_FC_GMD_PB3 … #define HDMI_FC_GMD_PB4 … #define HDMI_FC_GMD_PB5 … #define HDMI_FC_GMD_PB6 … #define HDMI_FC_GMD_PB7 … #define HDMI_FC_GMD_PB8 … #define HDMI_FC_GMD_PB9 … #define HDMI_FC_GMD_PB10 … #define HDMI_FC_GMD_PB11 … #define HDMI_FC_GMD_PB12 … #define HDMI_FC_GMD_PB13 … #define HDMI_FC_GMD_PB14 … #define HDMI_FC_GMD_PB15 … #define HDMI_FC_GMD_PB16 … #define HDMI_FC_GMD_PB17 … #define HDMI_FC_GMD_PB18 … #define HDMI_FC_GMD_PB19 … #define HDMI_FC_GMD_PB20 … #define HDMI_FC_GMD_PB21 … #define HDMI_FC_GMD_PB22 … #define HDMI_FC_GMD_PB23 … #define HDMI_FC_GMD_PB24 … #define HDMI_FC_GMD_PB25 … #define HDMI_FC_GMD_PB26 … #define HDMI_FC_GMD_PB27 … #define HDMI_FC_DRM_UP … #define HDMI_FC_DRM_HB0 … #define HDMI_FC_DRM_HB1 … #define HDMI_FC_DRM_PB0 … #define HDMI_FC_DRM_PB1 … #define HDMI_FC_DRM_PB2 … #define HDMI_FC_DRM_PB3 … #define HDMI_FC_DRM_PB4 … #define HDMI_FC_DRM_PB5 … #define HDMI_FC_DRM_PB6 … #define HDMI_FC_DRM_PB7 … #define HDMI_FC_DRM_PB8 … #define HDMI_FC_DRM_PB9 … #define HDMI_FC_DRM_PB10 … #define HDMI_FC_DRM_PB11 … #define HDMI_FC_DRM_PB12 … #define HDMI_FC_DRM_PB13 … #define HDMI_FC_DRM_PB14 … #define HDMI_FC_DRM_PB15 … #define HDMI_FC_DRM_PB16 … #define HDMI_FC_DRM_PB17 … #define HDMI_FC_DRM_PB18 … #define HDMI_FC_DRM_PB19 … #define HDMI_FC_DRM_PB20 … #define HDMI_FC_DRM_PB21 … #define HDMI_FC_DRM_PB22 … #define HDMI_FC_DRM_PB23 … #define HDMI_FC_DRM_PB24 … #define HDMI_FC_DRM_PB25 … #define HDMI_FC_DRM_PB26 … #define HDMI_FC_DBGFORCE … #define HDMI_FC_DBGAUD0CH0 … #define HDMI_FC_DBGAUD1CH0 … #define HDMI_FC_DBGAUD2CH0 … #define HDMI_FC_DBGAUD0CH1 … #define HDMI_FC_DBGAUD1CH1 … #define HDMI_FC_DBGAUD2CH1 … #define HDMI_FC_DBGAUD0CH2 … #define HDMI_FC_DBGAUD1CH2 … #define HDMI_FC_DBGAUD2CH2 … #define HDMI_FC_DBGAUD0CH3 … #define HDMI_FC_DBGAUD1CH3 … #define HDMI_FC_DBGAUD2CH3 … #define HDMI_FC_DBGAUD0CH4 … #define HDMI_FC_DBGAUD1CH4 … #define HDMI_FC_DBGAUD2CH4 … #define HDMI_FC_DBGAUD0CH5 … #define HDMI_FC_DBGAUD1CH5 … #define HDMI_FC_DBGAUD2CH5 … #define HDMI_FC_DBGAUD0CH6 … #define HDMI_FC_DBGAUD1CH6 … #define HDMI_FC_DBGAUD2CH6 … #define HDMI_FC_DBGAUD0CH7 … #define HDMI_FC_DBGAUD1CH7 … #define HDMI_FC_DBGAUD2CH7 … #define HDMI_FC_DBGTMDS0 … #define HDMI_FC_DBGTMDS1 … #define HDMI_FC_DBGTMDS2 … /* HDMI Source PHY Registers */ #define HDMI_PHY_CONF0 … #define HDMI_PHY_TST0 … #define HDMI_PHY_TST1 … #define HDMI_PHY_TST2 … #define HDMI_PHY_STAT0 … #define HDMI_PHY_INT0 … #define HDMI_PHY_MASK0 … #define HDMI_PHY_POL0 … /* HDMI Master PHY Registers */ #define HDMI_PHY_I2CM_SLAVE_ADDR … #define HDMI_PHY_I2CM_ADDRESS_ADDR … #define HDMI_PHY_I2CM_DATAO_1_ADDR … #define HDMI_PHY_I2CM_DATAO_0_ADDR … #define HDMI_PHY_I2CM_DATAI_1_ADDR … #define HDMI_PHY_I2CM_DATAI_0_ADDR … #define HDMI_PHY_I2CM_OPERATION_ADDR … #define HDMI_PHY_I2CM_INT_ADDR … #define HDMI_PHY_I2CM_CTLINT_ADDR … #define HDMI_PHY_I2CM_DIV_ADDR … #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR … #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR … #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR … #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR … #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR … #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR … #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR … #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR … #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR … /* Audio Sampler Registers */ #define HDMI_AUD_CONF0 … #define HDMI_AUD_CONF1 … #define HDMI_AUD_INT … #define HDMI_AUD_CONF2 … #define HDMI_AUD_N1 … #define HDMI_AUD_N2 … #define HDMI_AUD_N3 … #define HDMI_AUD_CTS1 … #define HDMI_AUD_CTS2 … #define HDMI_AUD_CTS3 … #define HDMI_AUD_INPUTCLKFS … #define HDMI_AUD_SPDIFINT … #define HDMI_AUD_CONF0_HBR … #define HDMI_AUD_HBR_STATUS … #define HDMI_AUD_HBR_INT … #define HDMI_AUD_HBR_POL … #define HDMI_AUD_HBR_MASK … /* * Generic Parallel Audio Interface Registers * Not used as GPAUD interface is not enabled in hw */ #define HDMI_GP_CONF0 … #define HDMI_GP_CONF1 … #define HDMI_GP_CONF2 … #define HDMI_GP_STAT … #define HDMI_GP_INT … #define HDMI_GP_MASK … #define HDMI_GP_POL … /* Audio DMA Registers */ #define HDMI_AHB_DMA_CONF0 … #define HDMI_AHB_DMA_START … #define HDMI_AHB_DMA_STOP … #define HDMI_AHB_DMA_THRSLD … #define HDMI_AHB_DMA_STRADDR0 … #define HDMI_AHB_DMA_STRADDR1 … #define HDMI_AHB_DMA_STRADDR2 … #define HDMI_AHB_DMA_STRADDR3 … #define HDMI_AHB_DMA_STPADDR0 … #define HDMI_AHB_DMA_STPADDR1 … #define HDMI_AHB_DMA_STPADDR2 … #define HDMI_AHB_DMA_STPADDR3 … #define HDMI_AHB_DMA_BSTADDR0 … #define HDMI_AHB_DMA_BSTADDR1 … #define HDMI_AHB_DMA_BSTADDR2 … #define HDMI_AHB_DMA_BSTADDR3 … #define HDMI_AHB_DMA_MBLENGTH0 … #define HDMI_AHB_DMA_MBLENGTH1 … #define HDMI_AHB_DMA_STAT … #define HDMI_AHB_DMA_INT … #define HDMI_AHB_DMA_MASK … #define HDMI_AHB_DMA_POL … #define HDMI_AHB_DMA_CONF1 … #define HDMI_AHB_DMA_BUFFSTAT … #define HDMI_AHB_DMA_BUFFINT … #define HDMI_AHB_DMA_BUFFMASK … #define HDMI_AHB_DMA_BUFFPOL … /* Main Controller Registers */ #define HDMI_MC_SFRDIV … #define HDMI_MC_CLKDIS … #define HDMI_MC_SWRSTZ … #define HDMI_MC_OPCTRL … #define HDMI_MC_FLOWCTRL … #define HDMI_MC_PHYRSTZ … #define HDMI_MC_LOCKONCLOCK … #define HDMI_MC_HEACPHY_RST … /* Color Space Converter Registers */ #define HDMI_CSC_CFG … #define HDMI_CSC_SCALE … #define HDMI_CSC_COEF_A1_MSB … #define HDMI_CSC_COEF_A1_LSB … #define HDMI_CSC_COEF_A2_MSB … #define HDMI_CSC_COEF_A2_LSB … #define HDMI_CSC_COEF_A3_MSB … #define HDMI_CSC_COEF_A3_LSB … #define HDMI_CSC_COEF_A4_MSB … #define HDMI_CSC_COEF_A4_LSB … #define HDMI_CSC_COEF_B1_MSB … #define HDMI_CSC_COEF_B1_LSB … #define HDMI_CSC_COEF_B2_MSB … #define HDMI_CSC_COEF_B2_LSB … #define HDMI_CSC_COEF_B3_MSB … #define HDMI_CSC_COEF_B3_LSB … #define HDMI_CSC_COEF_B4_MSB … #define HDMI_CSC_COEF_B4_LSB … #define HDMI_CSC_COEF_C1_MSB … #define HDMI_CSC_COEF_C1_LSB … #define HDMI_CSC_COEF_C2_MSB … #define HDMI_CSC_COEF_C2_LSB … #define HDMI_CSC_COEF_C3_MSB … #define HDMI_CSC_COEF_C3_LSB … #define HDMI_CSC_COEF_C4_MSB … #define HDMI_CSC_COEF_C4_LSB … /* HDCP Encryption Engine Registers */ #define HDMI_A_HDCPCFG0 … #define HDMI_A_HDCPCFG1 … #define HDMI_A_HDCPOBS0 … #define HDMI_A_HDCPOBS1 … #define HDMI_A_HDCPOBS2 … #define HDMI_A_HDCPOBS3 … #define HDMI_A_APIINTCLR … #define HDMI_A_APIINTSTAT … #define HDMI_A_APIINTMSK … #define HDMI_A_VIDPOLCFG … #define HDMI_A_OESSWCFG … #define HDMI_A_TIMER1SETUP0 … #define HDMI_A_TIMER1SETUP1 … #define HDMI_A_TIMER2SETUP0 … #define HDMI_A_TIMER2SETUP1 … #define HDMI_A_100MSCFG … #define HDMI_A_2SCFG0 … #define HDMI_A_2SCFG1 … #define HDMI_A_5SCFG0 … #define HDMI_A_5SCFG1 … #define HDMI_A_SRMVERLSB … #define HDMI_A_SRMVERMSB … #define HDMI_A_SRMCTRL … #define HDMI_A_SFRSETUP … #define HDMI_A_I2CHSETUP … #define HDMI_A_INTSETUP … #define HDMI_A_PRESETUP … #define HDMI_A_SRM_BASE … /* I2C Master Registers (E-DDC) */ #define HDMI_I2CM_SLAVE … #define HDMI_I2CM_ADDRESS … #define HDMI_I2CM_DATAO … #define HDMI_I2CM_DATAI … #define HDMI_I2CM_OPERATION … #define HDMI_I2CM_INT … #define HDMI_I2CM_CTLINT … #define HDMI_I2CM_DIV … #define HDMI_I2CM_SEGADDR … #define HDMI_I2CM_SOFTRSTZ … #define HDMI_I2CM_SEGPTR … #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR … #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR … #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR … #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR … #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR … #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR … #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR … #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR … enum { … }; /* * HDMI 3D TX PHY registers */ #define HDMI_3D_TX_PHY_PWRCTRL … #define HDMI_3D_TX_PHY_SERDIVCTRL … #define HDMI_3D_TX_PHY_SERCKCTRL … #define HDMI_3D_TX_PHY_SERCKKILLCTRL … #define HDMI_3D_TX_PHY_TXRESCTRL … #define HDMI_3D_TX_PHY_CKCALCTRL … #define HDMI_3D_TX_PHY_CPCE_CTRL … #define HDMI_3D_TX_PHY_TXCLKMEASCTRL … #define HDMI_3D_TX_PHY_TXMEASCTRL … #define HDMI_3D_TX_PHY_CKSYMTXCTRL … #define HDMI_3D_TX_PHY_CMPSEQCTRL … #define HDMI_3D_TX_PHY_CMPPWRCTRL … #define HDMI_3D_TX_PHY_CMPMODECTRL … #define HDMI_3D_TX_PHY_MEASCTRL … #define HDMI_3D_TX_PHY_VLEVCTRL … #define HDMI_3D_TX_PHY_D2ACTRL … #define HDMI_3D_TX_PHY_CURRCTRL … #define HDMI_3D_TX_PHY_DRVANACTRL … #define HDMI_3D_TX_PHY_PLLMEASCTRL … #define HDMI_3D_TX_PHY_PLLPHBYCTRL … #define HDMI_3D_TX_PHY_GRP_CTRL … #define HDMI_3D_TX_PHY_GMPCTRL … #define HDMI_3D_TX_PHY_MPLLMEASCTRL … #define HDMI_3D_TX_PHY_MSM_CTRL … #define HDMI_3D_TX_PHY_SCRPB_STATUS … #define HDMI_3D_TX_PHY_TXTERM … #define HDMI_3D_TX_PHY_PTRPT_ENBL … #define HDMI_3D_TX_PHY_PATTERNGEN … #define HDMI_3D_TX_PHY_SDCAP_MODE … #define HDMI_3D_TX_PHY_SCOPEMODE … #define HDMI_3D_TX_PHY_DIGTXMODE … #define HDMI_3D_TX_PHY_STR_STATUS … #define HDMI_3D_TX_PHY_SCOPECNT0 … #define HDMI_3D_TX_PHY_SCOPECNT1 … #define HDMI_3D_TX_PHY_SCOPECNT2 … #define HDMI_3D_TX_PHY_SCOPECNTCLK … #define HDMI_3D_TX_PHY_SCOPESAMPLE … #define HDMI_3D_TX_PHY_SCOPECNTMSB01 … #define HDMI_3D_TX_PHY_SCOPECNTMSB2CK … /* HDMI_3D_TX_PHY_CKCALCTRL values */ #define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE … /* HDMI_3D_TX_PHY_MSM_CTRL values */ #define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK … #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL … #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF … #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK … #define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK … #define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL … /* HDMI_3D_TX_PHY_PTRPT_ENBL values */ #define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE … #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 … #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 … #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 … #define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB … #define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB … #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB … #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY … #define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB … #define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB … #endif /* __DW_HDMI_H__ */
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