// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd * Copyright (C) STMicroelectronics SA 2017 * * Modified by Philippe Cornu <[email protected]> * This generic Synopsys DesignWare MIPI DSI host driver is based on the * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. */ #include <linux/clk.h> #include <linux/component.h> #include <linux/debugfs.h> #include <linux/iopoll.h> #include <linux/math64.h> #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <video/mipi_display.h> #include <drm/bridge/dw_mipi_dsi.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_bridge.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_modes.h> #include <drm/drm_of.h> #include <drm/drm_print.h> #define HWVER_131 … #define DSI_VERSION … #define VERSION … #define DSI_PWR_UP … #define RESET … #define POWERUP … #define DSI_CLKMGR_CFG … #define TO_CLK_DIVISION(div) … #define TX_ESC_CLK_DIVISION(div) … #define DSI_DPI_VCID … #define DPI_VCID(vcid) … #define DSI_DPI_COLOR_CODING … #define LOOSELY18_EN … #define DPI_COLOR_CODING_16BIT_1 … #define DPI_COLOR_CODING_16BIT_2 … #define DPI_COLOR_CODING_16BIT_3 … #define DPI_COLOR_CODING_18BIT_1 … #define DPI_COLOR_CODING_18BIT_2 … #define DPI_COLOR_CODING_24BIT … #define DSI_DPI_CFG_POL … #define COLORM_ACTIVE_LOW … #define SHUTD_ACTIVE_LOW … #define HSYNC_ACTIVE_LOW … #define VSYNC_ACTIVE_LOW … #define DATAEN_ACTIVE_LOW … #define DSI_DPI_LP_CMD_TIM … #define OUTVACT_LPCMD_TIME(p) … #define INVACT_LPCMD_TIME(p) … #define DSI_DBI_VCID … #define DSI_DBI_CFG … #define DSI_DBI_PARTITIONING_EN … #define DSI_DBI_CMDSIZE … #define DSI_PCKHDL_CFG … #define CRC_RX_EN … #define ECC_RX_EN … #define BTA_EN … #define EOTP_RX_EN … #define EOTP_TX_EN … #define DSI_GEN_VCID … #define DSI_MODE_CFG … #define ENABLE_VIDEO_MODE … #define ENABLE_CMD_MODE … #define DSI_VID_MODE_CFG … #define ENABLE_LOW_POWER … #define ENABLE_LOW_POWER_MASK … #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES … #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS … #define VID_MODE_TYPE_BURST … #define VID_MODE_TYPE_MASK … #define ENABLE_LOW_POWER_CMD … #define VID_MODE_VPG_ENABLE … #define VID_MODE_VPG_MODE … #define VID_MODE_VPG_HORIZONTAL … #define DSI_VID_PKT_SIZE … #define VID_PKT_SIZE(p) … #define DSI_VID_NUM_CHUNKS … #define VID_NUM_CHUNKS(c) … #define DSI_VID_NULL_SIZE … #define VID_NULL_SIZE(b) … #define DSI_VID_HSA_TIME … #define DSI_VID_HBP_TIME … #define DSI_VID_HLINE_TIME … #define DSI_VID_VSA_LINES … #define DSI_VID_VBP_LINES … #define DSI_VID_VFP_LINES … #define DSI_VID_VACTIVE_LINES … #define DSI_EDPI_CMD_SIZE … #define DSI_CMD_MODE_CFG … #define MAX_RD_PKT_SIZE_LP … #define DCS_LW_TX_LP … #define DCS_SR_0P_TX_LP … #define DCS_SW_1P_TX_LP … #define DCS_SW_0P_TX_LP … #define GEN_LW_TX_LP … #define GEN_SR_2P_TX_LP … #define GEN_SR_1P_TX_LP … #define GEN_SR_0P_TX_LP … #define GEN_SW_2P_TX_LP … #define GEN_SW_1P_TX_LP … #define GEN_SW_0P_TX_LP … #define ACK_RQST_EN … #define TEAR_FX_EN … #define CMD_MODE_ALL_LP … #define DSI_GEN_HDR … #define DSI_GEN_PLD_DATA … #define DSI_CMD_PKT_STATUS … #define GEN_RD_CMD_BUSY … #define GEN_PLD_R_FULL … #define GEN_PLD_R_EMPTY … #define GEN_PLD_W_FULL … #define GEN_PLD_W_EMPTY … #define GEN_CMD_FULL … #define GEN_CMD_EMPTY … #define DSI_TO_CNT_CFG … #define HSTX_TO_CNT(p) … #define LPRX_TO_CNT(p) … #define DSI_HS_RD_TO_CNT … #define DSI_LP_RD_TO_CNT … #define DSI_HS_WR_TO_CNT … #define DSI_LP_WR_TO_CNT … #define DSI_BTA_TO_CNT … #define DSI_LPCLK_CTRL … #define AUTO_CLKLANE_CTRL … #define PHY_TXREQUESTCLKHS … #define DSI_PHY_TMR_LPCLK_CFG … #define PHY_CLKHS2LP_TIME(lbcc) … #define PHY_CLKLP2HS_TIME(lbcc) … #define DSI_PHY_TMR_CFG … #define PHY_HS2LP_TIME(lbcc) … #define PHY_LP2HS_TIME(lbcc) … #define MAX_RD_TIME(lbcc) … #define PHY_HS2LP_TIME_V131(lbcc) … #define PHY_LP2HS_TIME_V131(lbcc) … #define DSI_PHY_RSTZ … #define PHY_DISFORCEPLL … #define PHY_ENFORCEPLL … #define PHY_DISABLECLK … #define PHY_ENABLECLK … #define PHY_RSTZ … #define PHY_UNRSTZ … #define PHY_SHUTDOWNZ … #define PHY_UNSHUTDOWNZ … #define DSI_PHY_IF_CFG … #define PHY_STOP_WAIT_TIME(cycle) … #define N_LANES(n) … #define DSI_PHY_ULPS_CTRL … #define DSI_PHY_TX_TRIGGERS … #define DSI_PHY_STATUS … #define PHY_STOP_STATE_CLK_LANE … #define PHY_LOCK … #define DSI_PHY_TST_CTRL0 … #define PHY_TESTCLK … #define PHY_UNTESTCLK … #define PHY_TESTCLR … #define PHY_UNTESTCLR … #define DSI_PHY_TST_CTRL1 … #define PHY_TESTEN … #define PHY_UNTESTEN … #define PHY_TESTDOUT(n) … #define PHY_TESTDIN(n) … #define DSI_INT_ST0 … #define DSI_INT_ST1 … #define DSI_INT_MSK0 … #define DSI_INT_MSK1 … #define DSI_PHY_TMR_RD_CFG … #define MAX_RD_TIME_V131(lbcc) … #define PHY_STATUS_TIMEOUT_US … #define CMD_PKT_STATUS_TIMEOUT_US … #ifdef CONFIG_DEBUG_FS #define VPG_DEFS(name, dsi) … #define REGISTER(name, mask, dsi) … struct debugfs_entries { … }; #endif /* CONFIG_DEBUG_FS */ struct dw_mipi_dsi { … }; /* * Check if either a link to a master or slave is present */ static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) { … } /* * The controller should generate 2 frames before * preparing the peripheral. */ static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) { … } static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) { … } static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) { … } static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) { … } static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) { … } static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { … } static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { … } static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, const struct mipi_dsi_msg *msg) { … } static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) { … } static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, const struct mipi_dsi_packet *packet) { … } static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, const struct mipi_dsi_msg *msg) { … } static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg) { … } static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = …; static u32 * dw_mipi_dsi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts) { … } static int dw_mipi_dsi_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, unsigned long mode_flags) { … } static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode) { … } static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode) { … } static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) { … } static const u32 minimum_lbccs[] = …; static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi) { … } /* Get lane byte clock cycles. */ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode, u32 hcomponent) { … } static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode) { … } static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode) { … } static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { … } static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, const struct drm_display_mode *adjusted_mode) { … } static void dw_mipi_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { … } static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) { … } static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { … } static enum drm_mode_status dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { … } static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { … } static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = …; #ifdef CONFIG_DEBUG_FS static int dw_mipi_dsi_debugfs_write(void *data, u64 val) { … } static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static void debugfs_create_files(void *data) { … } static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { … } static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { … } #else static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { } static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } #endif /* CONFIG_DEBUG_FS */ static struct dw_mipi_dsi * __dw_mipi_dsi_probe(struct platform_device *pdev, const struct dw_mipi_dsi_plat_data *plat_data) { … } static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) { … } void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) { … } EXPORT_SYMBOL_GPL(…); struct drm_bridge *dw_mipi_dsi_get_bridge(struct dw_mipi_dsi *dsi) { … } EXPORT_SYMBOL_GPL(…); /* * Probe/remove API, used from platforms based on the DRM bridge API. */ struct dw_mipi_dsi * dw_mipi_dsi_probe(struct platform_device *pdev, const struct dw_mipi_dsi_plat_data *plat_data) { … } EXPORT_SYMBOL_GPL(…); void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) { … } EXPORT_SYMBOL_GPL(…); /* * Bind/unbind API, used from platforms based on the component framework. */ int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) { … } EXPORT_SYMBOL_GPL(…); void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) { … } EXPORT_SYMBOL_GPL(…); MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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