/* SPDX-License-Identifier: GPL-2.0-only */ /* * Registers of Silicon Image SiI8620 Mobile HD Transmitter * * Copyright (C) 2015, Samsung Electronics Co., Ltd. * Andrzej Hajda <[email protected]> * * Based on MHL driver for Android devices. * Copyright (C) 2013-2014 Silicon Image, Inc. */ #ifndef __SIL_SII8620_H__ #define __SIL_SII8620_H__ /* Vendor ID Low byte, default value: 0x01 */ #define REG_VND_IDL … /* Vendor ID High byte, default value: 0x00 */ #define REG_VND_IDH … /* Device ID Low byte, default value: 0x60 */ #define REG_DEV_IDL … /* Device ID High byte, default value: 0x86 */ #define REG_DEV_IDH … /* Device Revision, default value: 0x10 */ #define REG_DEV_REV … /* OTP DBYTE510, default value: 0x00 */ #define REG_OTP_DBYTE510 … /* System Control #1, default value: 0x00 */ #define REG_SYS_CTRL1 … #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET … #define BIT_SYS_CTRL1_VSYNCPIN … #define BIT_SYS_CTRL1_OTPADROPOVR_SET … #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD … #define BIT_SYS_CTRL1_OTP2XVOVR_EN … #define BIT_SYS_CTRL1_OTP2XAOVR_EN … #define BIT_SYS_CTRL1_TX_CTRL_HDMI … #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET … /* System Control DPD, default value: 0x90 */ #define REG_DPD … #define BIT_DPD_PWRON_PLL … #define BIT_DPD_PDNTX12 … #define BIT_DPD_PDNRX12 … #define BIT_DPD_OSC_EN … #define BIT_DPD_PWRON_HSIC … #define BIT_DPD_PDIDCK_N … #define BIT_DPD_PD_MHL_CLK_N … /* Dual link Control, default value: 0x00 */ #define REG_DCTL … #define BIT_DCTL_TDM_LCLK_PHASE … #define BIT_DCTL_HSIC_CLK_PHASE … #define BIT_DCTL_CTS_TCK_PHASE … #define BIT_DCTL_EXT_DDC_SEL … #define BIT_DCTL_TRANSCODE … #define BIT_DCTL_HSIC_RX_STROBE_PHASE … #define BIT_DCTL_HSIC_TX_BIST_START_SEL … #define BIT_DCTL_TCLKNX_PHASE … /* PWD Software Reset, default value: 0x20 */ #define REG_PWD_SRST … #define BIT_PWD_SRST_COC_DOC_RST … #define BIT_PWD_SRST_CBUS_RST_SW … #define BIT_PWD_SRST_CBUS_RST_SW_EN … #define BIT_PWD_SRST_MHLFIFO_RST … #define BIT_PWD_SRST_CBUS_RST … #define BIT_PWD_SRST_SW_RST_AUTO … #define BIT_PWD_SRST_HDCP2X_SW_RST … #define BIT_PWD_SRST_SW_RST … /* AKSV_1, default value: 0x00 */ #define REG_AKSV_1 … /* Video H Resolution #1, default value: 0x00 */ #define REG_H_RESL … /* Video Mode, default value: 0x00 */ #define REG_VID_MODE … #define BIT_VID_MODE_M1080P … /* Video Input Mode, default value: 0xc0 */ #define REG_VID_OVRRD … #define BIT_VID_OVRRD_PP_AUTO_DISABLE … #define BIT_VID_OVRRD_M1080P_OVRRD … #define BIT_VID_OVRRD_MINIVSYNC_ON … #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK … #define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN … #define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD … #define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD … /* I2C Address reassignment, default value: 0x00 */ #define REG_PAGE_MHLSPEC_ADDR … #define REG_PAGE7_ADDR … #define REG_PAGE8_ADDR … /* Fast Interrupt Status, default value: 0x00 */ #define REG_FAST_INTR_STAT … #define LEN_FAST_INTR_STAT … #define BIT_FAST_INTR_STAT_TIMR … #define BIT_FAST_INTR_STAT_INT2 … #define BIT_FAST_INTR_STAT_DDC … #define BIT_FAST_INTR_STAT_SCDT … #define BIT_FAST_INTR_STAT_INFR … #define BIT_FAST_INTR_STAT_EDID … #define BIT_FAST_INTR_STAT_HDCP … #define BIT_FAST_INTR_STAT_MSC … #define BIT_FAST_INTR_STAT_MERR … #define BIT_FAST_INTR_STAT_G2WB … #define BIT_FAST_INTR_STAT_G2WB_ERR … #define BIT_FAST_INTR_STAT_DISC … #define BIT_FAST_INTR_STAT_BLOCK … #define BIT_FAST_INTR_STAT_LTRN … #define BIT_FAST_INTR_STAT_HDCP2 … #define BIT_FAST_INTR_STAT_TDM … #define BIT_FAST_INTR_STAT_COC … /* GPIO Control, default value: 0x15 */ #define REG_GPIO_CTRL1 … #define BIT_CTRL1_GPIO_I_8 … #define BIT_CTRL1_GPIO_OEN_8 … #define BIT_CTRL1_GPIO_I_7 … #define BIT_CTRL1_GPIO_OEN_7 … #define BIT_CTRL1_GPIO_I_6 … #define BIT_CTRL1_GPIO_OEN_6 … /* Interrupt Control, default value: 0x06 */ #define REG_INT_CTRL … #define BIT_INT_CTRL_SOFTWARE_WP … #define BIT_INT_CTRL_INTR_OD … #define BIT_INT_CTRL_INTR_POLARITY … /* Interrupt State, default value: 0x00 */ #define REG_INTR_STATE … #define BIT_INTR_STATE_INTR_STATE … /* Interrupt Source #1, default value: 0x00 */ #define REG_INTR1 … /* Interrupt Source #2, default value: 0x00 */ #define REG_INTR2 … /* Interrupt Source #3, default value: 0x01 */ #define REG_INTR3 … #define BIT_DDC_CMD_DONE … /* Interrupt Source #5, default value: 0x00 */ #define REG_INTR5 … /* Interrupt #1 Mask, default value: 0x00 */ #define REG_INTR1_MASK … /* Interrupt #2 Mask, default value: 0x00 */ #define REG_INTR2_MASK … /* Interrupt #3 Mask, default value: 0x00 */ #define REG_INTR3_MASK … /* Interrupt #5 Mask, default value: 0x00 */ #define REG_INTR5_MASK … #define BIT_INTR_SCDT_CHANGE … /* Hot Plug Connection Control, default value: 0x45 */ #define REG_HPD_CTRL … #define BIT_HPD_CTRL_HPD_DS_SIGNAL … #define BIT_HPD_CTRL_HPD_OUT_OD_EN … #define BIT_HPD_CTRL_HPD_HIGH … #define BIT_HPD_CTRL_HPD_OUT_OVR_EN … #define BIT_HPD_CTRL_GPIO_I_1 … #define BIT_HPD_CTRL_GPIO_OEN_1 … #define BIT_HPD_CTRL_GPIO_I_0 … #define BIT_HPD_CTRL_GPIO_OEN_0 … /* GPIO Control, default value: 0x55 */ #define REG_GPIO_CTRL … #define BIT_CTRL_GPIO_I_5 … #define BIT_CTRL_GPIO_OEN_5 … #define BIT_CTRL_GPIO_I_4 … #define BIT_CTRL_GPIO_OEN_4 … #define BIT_CTRL_GPIO_I_3 … #define BIT_CTRL_GPIO_OEN_3 … #define BIT_CTRL_GPIO_I_2 … #define BIT_CTRL_GPIO_OEN_2 … /* Interrupt Source 7, default value: 0x00 */ #define REG_INTR7 … /* Interrupt Source 8, default value: 0x00 */ #define REG_INTR8 … /* Interrupt #7 Mask, default value: 0x00 */ #define REG_INTR7_MASK … /* Interrupt #8 Mask, default value: 0x00 */ #define REG_INTR8_MASK … #define BIT_CEA_NEW_VSI … #define BIT_CEA_NEW_AVI … /* IEEE, default value: 0x10 */ #define REG_TMDS_CCTRL … #define BIT_TMDS_CCTRL_TMDS_OE … /* TMDS Control #4, default value: 0x02 */ #define REG_TMDS_CTRL4 … #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL … #define BIT_TMDS_CTRL4_TX_EN_BY_SCDT … /* BIST CNTL, default value: 0x00 */ #define REG_BIST_CTRL … #define BIT_RXBIST_VGB_EN … #define BIT_TXBIST_VGB_EN … #define BIT_BIST_START_SEL … #define BIT_BIST_START_BIT … #define BIT_BIST_ALWAYS_ON … #define BIT_BIST_TRANS … #define BIT_BIST_RESET … #define BIT_BIST_EN … /* BIST DURATION0, default value: 0x00 */ #define REG_BIST_TEST_SEL … #define MSK_BIST_TEST_SEL_BIST_PATT_SEL … /* BIST VIDEO_MODE, default value: 0x00 */ #define REG_BIST_VIDEO_MODE … #define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 … /* BIST DURATION0, default value: 0x00 */ #define REG_BIST_DURATION_0 … /* BIST DURATION1, default value: 0x00 */ #define REG_BIST_DURATION_1 … /* BIST DURATION2, default value: 0x00 */ #define REG_BIST_DURATION_2 … /* BIST 8BIT_PATTERN, default value: 0x00 */ #define REG_BIST_8BIT_PATTERN … /* LM DDC, default value: 0x80 */ #define REG_LM_DDC … #define BIT_LM_DDC_SW_TPI_EN_DISABLED … #define BIT_LM_DDC_VIDEO_MUTE_EN … #define BIT_LM_DDC_DDC_TPI_SW … #define BIT_LM_DDC_DDC_GRANT … #define BIT_LM_DDC_DDC_GPU_REQUEST … /* DDC I2C Manual, default value: 0x03 */ #define REG_DDC_MANUAL … #define BIT_DDC_MANUAL_MAN_DDC … #define BIT_DDC_MANUAL_VP_SEL … #define BIT_DDC_MANUAL_DSDA … #define BIT_DDC_MANUAL_DSCL … #define BIT_DDC_MANUAL_GCP_HW_CTL_EN … #define BIT_DDC_MANUAL_DDCM_ABORT_WP … #define BIT_DDC_MANUAL_IO_DSDA … #define BIT_DDC_MANUAL_IO_DSCL … /* DDC I2C Target Slave Address, default value: 0x00 */ #define REG_DDC_ADDR … #define MSK_DDC_ADDR_DDC_ADDR … /* DDC I2C Target Segment Address, default value: 0x00 */ #define REG_DDC_SEGM … /* DDC I2C Target Offset Address, default value: 0x00 */ #define REG_DDC_OFFSET … /* DDC I2C Data In count #1, default value: 0x00 */ #define REG_DDC_DIN_CNT1 … /* DDC I2C Data In count #2, default value: 0x00 */ #define REG_DDC_DIN_CNT2 … #define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 … /* DDC I2C Status, default value: 0x04 */ #define REG_DDC_STATUS … #define BIT_DDC_STATUS_DDC_BUS_LOW … #define BIT_DDC_STATUS_DDC_NO_ACK … #define BIT_DDC_STATUS_DDC_I2C_IN_PROG … #define BIT_DDC_STATUS_DDC_FIFO_FULL … #define BIT_DDC_STATUS_DDC_FIFO_EMPTY … #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE … #define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE … /* DDC I2C Command, default value: 0x70 */ #define REG_DDC_CMD … #define BIT_DDC_CMD_HDCP_DDC_EN … #define BIT_DDC_CMD_SDA_DEL_EN … #define BIT_DDC_CMD_DDC_FLT_EN … #define MSK_DDC_CMD_DDC_CMD … #define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK … #define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO … #define VAL_DDC_CMD_DDC_CMD_ABORT … /* DDC I2C FIFO Data In/Out, default value: 0x00 */ #define REG_DDC_DATA … /* DDC I2C Data Out Counter, default value: 0x00 */ #define REG_DDC_DOUT_CNT … #define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 … #define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT … /* DDC I2C Delay Count, default value: 0x14 */ #define REG_DDC_DELAY_CNT … /* Test Control, default value: 0x80 */ #define REG_TEST_TXCTRL … #define BIT_TEST_TXCTRL_RCLK_REF_SEL … #define BIT_TEST_TXCTRL_PCLK_REF_SEL … #define MSK_TEST_TXCTRL_BYPASS_PLL_CLK … #define BIT_TEST_TXCTRL_HDMI_MODE … #define BIT_TEST_TXCTRL_TST_PLLCK … /* CBUS Address, default value: 0x00 */ #define REG_PAGE_CBUS_ADDR … /* I2C Device Address re-assignment */ #define REG_PAGE1_ADDR … #define REG_PAGE2_ADDR … #define REG_PAGE3_ADDR … #define REG_HW_TPI_ADDR … /* USBT CTRL0, default value: 0x00 */ #define REG_UTSRST … #define BIT_UTSRST_FC_SRST … #define BIT_UTSRST_KEEPER_SRST … #define BIT_UTSRST_HTX_SRST … #define BIT_UTSRST_TRX_SRST … #define BIT_UTSRST_TTX_SRST … #define BIT_UTSRST_HRX_SRST … /* HSIC RX Control3, default value: 0x07 */ #define REG_HRXCTRL3 … #define MSK_HRXCTRL3_HRX_AFFCTRL … #define BIT_HRXCTRL3_HRX_OUT_EN … #define BIT_HRXCTRL3_STATUS_EN … #define BIT_HRXCTRL3_HRX_STAY_RESET … /* HSIC RX INT Registers */ #define REG_HRXINTL … #define REG_HRXINTH … /* TDM TX NUMBITS, default value: 0x0c */ #define REG_TTXNUMB … #define MSK_TTXNUMB_TTX_AFFCTRL_3_0 … #define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT … #define MSK_TTXNUMB_TTX_NUMBPS … /* TDM TX NUMSPISYM, default value: 0x04 */ #define REG_TTXSPINUMS … /* TDM TX NUMHSICSYM, default value: 0x14 */ #define REG_TTXHSICNUMS … /* TDM TX NUMTOTSYM, default value: 0x18 */ #define REG_TTXTOTNUMS … /* TDM TX INT Low, default value: 0x00 */ #define REG_TTXINTL … #define BIT_TTXINTL_TTX_INTR7 … #define BIT_TTXINTL_TTX_INTR6 … #define BIT_TTXINTL_TTX_INTR5 … #define BIT_TTXINTL_TTX_INTR4 … #define BIT_TTXINTL_TTX_INTR3 … #define BIT_TTXINTL_TTX_INTR2 … #define BIT_TTXINTL_TTX_INTR1 … #define BIT_TTXINTL_TTX_INTR0 … /* TDM TX INT High, default value: 0x00 */ #define REG_TTXINTH … #define BIT_TTXINTH_TTX_INTR15 … #define BIT_TTXINTH_TTX_INTR14 … #define BIT_TTXINTH_TTX_INTR13 … #define BIT_TTXINTH_TTX_INTR12 … #define BIT_TTXINTH_TTX_INTR11 … #define BIT_TTXINTH_TTX_INTR10 … #define BIT_TTXINTH_TTX_INTR9 … #define BIT_TTXINTH_TTX_INTR8 … /* TDM RX Control, default value: 0x1c */ #define REG_TRXCTRL … #define BIT_TRXCTRL_TRX_CLR_WVALLOW … #define BIT_TRXCTRL_TRX_FROM_SE_COC … #define MSK_TRXCTRL_TRX_NUMBPS_2_0 … /* TDM RX NUMSPISYM, default value: 0x04 */ #define REG_TRXSPINUMS … /* TDM RX NUMHSICSYM, default value: 0x14 */ #define REG_TRXHSICNUMS … /* TDM RX NUMTOTSYM, default value: 0x18 */ #define REG_TRXTOTNUMS … /* TDM RX Status 2nd, default value: 0x00 */ #define REG_TRXSTA2 … #define MSK_TDM_SYNCHRONIZED … #define VAL_TDM_SYNCHRONIZED … /* TDM RX INT Low, default value: 0x00 */ #define REG_TRXINTL … /* TDM RX INT High, default value: 0x00 */ #define REG_TRXINTH … #define BIT_TDM_INTR_SYNC_DATA … #define BIT_TDM_INTR_SYNC_WAIT … /* TDM RX INTMASK High, default value: 0x00 */ #define REG_TRXINTMH … /* HSIC TX CRTL, default value: 0x00 */ #define REG_HTXCTRL … #define BIT_HTXCTRL_HTX_ALLSBE_SOP … #define BIT_HTXCTRL_HTX_RGDINV_USB … #define BIT_HTXCTRL_HTX_RSPTDM_BUSY … #define BIT_HTXCTRL_HTX_DRVCONN1 … #define BIT_HTXCTRL_HTX_DRVRST1 … /* HSIC TX INT Low, default value: 0x00 */ #define REG_HTXINTL … /* HSIC TX INT High, default value: 0x00 */ #define REG_HTXINTH … /* HSIC Keeper, default value: 0x00 */ #define REG_KEEPER … #define MSK_KEEPER_MODE … #define VAL_KEEPER_MODE_HOST … #define VAL_KEEPER_MODE_DEVICE … /* HSIC Flow Control General, default value: 0x02 */ #define REG_FCGC … #define BIT_FCGC_HSIC_HOSTMODE … #define BIT_FCGC_HSIC_ENABLE … /* HSIC Flow Control CTR13, default value: 0xfc */ #define REG_FCCTR13 … /* HSIC Flow Control CTR14, default value: 0xff */ #define REG_FCCTR14 … /* HSIC Flow Control CTR15, default value: 0xff */ #define REG_FCCTR15 … /* HSIC Flow Control CTR50, default value: 0x03 */ #define REG_FCCTR50 … /* HSIC Flow Control INTR0, default value: 0x00 */ #define REG_FCINTR0 … #define REG_FCINTR1 … #define REG_FCINTR2 … #define REG_FCINTR3 … #define REG_FCINTR4 … #define REG_FCINTR5 … #define REG_FCINTR6 … #define REG_FCINTR7 … /* TDM Low Latency, default value: 0x20 */ #define REG_TDMLLCTL … #define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL … #define MSK_TDMLLCTL_TRX_LL_SEL_MODE … #define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL … #define BIT_TDMLLCTL_TTX_LL_TIE_LOW … #define BIT_TDMLLCTL_TTX_LL_SEL_MODE … /* TMDS 0 Clock Control, default value: 0x10 */ #define REG_TMDS0_CCTRL1 … #define MSK_TMDS0_CCTRL1_TEST_SEL … #define MSK_TMDS0_CCTRL1_CLK1X_CTL … /* TMDS Clock Enable, default value: 0x00 */ #define REG_TMDS_CLK_EN … #define BIT_TMDS_CLK_EN_CLK_EN … /* TMDS Channel Enable, default value: 0x00 */ #define REG_TMDS_CH_EN … #define BIT_TMDS_CH_EN_CH0_EN … #define BIT_TMDS_CH_EN_CH12_EN … /* BGR_BIAS, default value: 0x07 */ #define REG_BGR_BIAS … #define BIT_BGR_BIAS_BGR_EN … #define MSK_BGR_BIAS_BIAS_BGR_D … /* TMDS 0 Digital I2C BW, default value: 0x0a */ #define REG_ALICE0_BW_I2C … /* TMDS 0 Digital Zone Control, default value: 0xe0 */ #define REG_ALICE0_ZONE_CTRL … #define BIT_ALICE0_ZONE_CTRL_ICRST_N … #define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 … #define MSK_ALICE0_ZONE_CTRL_SZONE_I2C … #define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL … /* TMDS 0 Digital PLL Mode Control, default value: 0x00 */ #define REG_ALICE0_MODE_CTRL … #define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C … #define MSK_ALICE0_MODE_CTRL_DIV20_CTRL … /* MHL Tx Control 6th, default value: 0xa0 */ #define REG_MHLTX_CTL6 … #define MSK_MHLTX_CTL6_EMI_SEL … #define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 … /* Packet Filter0, default value: 0x00 */ #define REG_PKT_FILTER_0 … #define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT … #define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT … #define BIT_PKT_FILTER_0_DROP_MPEG_PKT … #define BIT_PKT_FILTER_0_DROP_SPIF_PKT … #define BIT_PKT_FILTER_0_DROP_AIF_PKT … #define BIT_PKT_FILTER_0_DROP_AVI_PKT … #define BIT_PKT_FILTER_0_DROP_CTS_PKT … #define BIT_PKT_FILTER_0_DROP_GCP_PKT … /* Packet Filter1, default value: 0x00 */ #define REG_PKT_FILTER_1 … #define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS … #define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS … #define BIT_PKT_FILTER_1_DROP_AUDIO_PKT … #define BIT_PKT_FILTER_1_DROP_GEN2_PKT … #define BIT_PKT_FILTER_1_DROP_GEN_PKT … #define BIT_PKT_FILTER_1_DROP_VSIF_PKT … /* TMDS Clock Status, default value: 0x10 */ #define REG_TMDS_CSTAT_P3 … #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE … #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE … #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP … #define BIT_TMDS_CSTAT_P3_CLR_AVI … #define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS … #define BIT_TMDS_CSTAT_P3_SCDT … #define BIT_TMDS_CSTAT_P3_CKDT … /* RX_HDMI Control, default value: 0x10 */ #define REG_RX_HDMI_CTRL0 … #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC … #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR … #define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE … #define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE … #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN … #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE … /* RX_HDMI Control, default value: 0x38 */ #define REG_RX_HDMI_CTRL2 … #define MSK_RX_HDMI_CTRL2_IDLE_CNT … #define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) … #define BIT_RX_HDMI_CTRL2_USE_AV_MUTE … #define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI … /* RX_HDMI Control, default value: 0x0f */ #define REG_RX_HDMI_CTRL3 … #define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN … /* rx_hdmi Clear Buffer, default value: 0x00 */ #define REG_RX_HDMI_CLR_BUFFER … #define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP … #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI … #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI … #define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN … #define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID … #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN … #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN … /* RX_HDMI VSI Header1, default value: 0x00 */ #define REG_RX_HDMI_MON_PKT_HEADER1 … /* RX_HDMI VSI MHL Monitor, default value: 0x3c */ #define REG_RX_HDMI_VSIF_MHL_MON … #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT … #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT … /* Interrupt Source 9, default value: 0x00 */ #define REG_INTR9 … #define BIT_INTR9_EDID_ERROR … #define BIT_INTR9_EDID_DONE … #define BIT_INTR9_DEVCAP_DONE … /* Interrupt 9 Mask, default value: 0x00 */ #define REG_INTR9_MASK … /* TPI CBUS Start, default value: 0x00 */ #define REG_TPI_CBUS_START … #define BIT_TPI_CBUS_START_RCP_REQ_START … #define BIT_TPI_CBUS_START_RCPK_REPLY_START … #define BIT_TPI_CBUS_START_RCPE_REPLY_START … #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START … #define BIT_TPI_CBUS_START_PUT_DCAPCHG_START … #define BIT_TPI_CBUS_START_PUT_DCAPRDY_START … #define BIT_TPI_CBUS_START_GET_EDID_START_0 … #define BIT_TPI_CBUS_START_GET_DEVCAP_START … /* EDID Control, default value: 0x10 */ #define REG_EDID_CTRL … #define BIT_EDID_CTRL_EDID_PRIME_VALID … #define BIT_EDID_CTRL_XDEVCAP_EN … #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP … #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO … #define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN … #define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL … #define BIT_EDID_CTRL_INVALID_BKSV … #define BIT_EDID_CTRL_EDID_MODE_EN … /* EDID FIFO Addr, default value: 0x00 */ #define REG_EDID_FIFO_ADDR … /* EDID FIFO Write Data, default value: 0x00 */ #define REG_EDID_FIFO_WR_DATA … /* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */ #define REG_EDID_FIFO_ADDR_MON … /* EDID FIFO Read Data, default value: 0x00 */ #define REG_EDID_FIFO_RD_DATA … /* EDID DDC Segment Pointer, default value: 0x00 */ #define REG_EDID_START_EXT … /* TX IP BIST CNTL and Status, default value: 0x00 */ #define REG_TX_IP_BIST_CNTLSTA … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN … #define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN … #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL … /* TX IP BIST INST LOW, default value: 0x00 */ #define REG_TX_IP_BIST_INST_LOW … #define REG_TX_IP_BIST_INST_HIGH … /* TX IP BIST PATTERN LOW, default value: 0x00 */ #define REG_TX_IP_BIST_PAT_LOW … #define REG_TX_IP_BIST_PAT_HIGH … /* TX IP BIST CONFIGURE LOW, default value: 0x00 */ #define REG_TX_IP_BIST_CONF_LOW … #define REG_TX_IP_BIST_CONF_HIGH … /* E-MSC General Control, default value: 0x80 */ #define REG_GENCTL … #define BIT_GENCTL_SPEC_TRANS_DIS … #define BIT_GENCTL_DIS_XMIT_ERR_STATE … #define BIT_GENCTL_SPI_MISO_EDGE … #define BIT_GENCTL_SPI_MOSI_EDGE … #define BIT_GENCTL_CLR_EMSC_RFIFO … #define BIT_GENCTL_CLR_EMSC_XFIFO … #define BIT_GENCTL_START_TRAIN_SEQ … #define BIT_GENCTL_EMSC_EN … /* E-MSC Comma ErrorCNT, default value: 0x03 */ #define REG_COMMECNT … #define BIT_COMMECNT_I2C_TO_EMSC_EN … #define MSK_COMMECNT_COMMA_CHAR_ERR_CNT … /* E-MSC RFIFO ByteCnt, default value: 0x00 */ #define REG_EMSCRFIFOBCNTL … #define REG_EMSCRFIFOBCNTH … /* SPI Burst Cnt Status, default value: 0x00 */ #define REG_SPIBURSTCNT … /* SPI Burst Status and SWRST, default value: 0x00 */ #define REG_SPIBURSTSTAT … #define BIT_SPIBURSTSTAT_SPI_HDCPRST … #define BIT_SPIBURSTSTAT_SPI_CBUSRST … #define BIT_SPIBURSTSTAT_SPI_SRST … #define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE … /* E-MSC 1st Interrupt, default value: 0x00 */ #define REG_EMSCINTR … #define BIT_EMSCINTR_EMSC_XFIFO_EMPTY … #define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT … #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR … #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR … #define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR … #define BIT_EMSCINTR_EMSC_XMIT_DONE … #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT … #define BIT_EMSCINTR_SPI_DVLD … /* E-MSC Interrupt Mask, default value: 0x00 */ #define REG_EMSCINTRMASK … /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */ #define REG_EMSC_XMIT_WRITE_PORT … /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */ #define REG_EMSC_RCV_READ_PORT … /* E-MSC 2nd Interrupt, default value: 0x00 */ #define REG_EMSCINTR1 … #define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR … /* E-MSC Interrupt Mask, default value: 0x00 */ #define REG_EMSCINTRMASK1 … #define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 … /* MHL Top Ctl, default value: 0x00 */ #define REG_MHL_TOP_CTL … #define BIT_MHL_TOP_CTL_MHL3_DOC_SEL … #define BIT_MHL_TOP_CTL_MHL_PP_SEL … #define MSK_MHL_TOP_CTL_IF_TIMING_CTL … /* MHL DataPath 1st Ctl, default value: 0xbc */ #define REG_MHL_DP_CTL0 … #define BIT_MHL_DP_CTL0_DP_OE … #define BIT_MHL_DP_CTL0_TX_OE_OVR … #define MSK_MHL_DP_CTL0_TX_OE … /* MHL DataPath 2nd Ctl, default value: 0xbb */ #define REG_MHL_DP_CTL1 … #define MSK_MHL_DP_CTL1_CK_SWING_CTL … #define MSK_MHL_DP_CTL1_DT_SWING_CTL … /* MHL DataPath 3rd Ctl, default value: 0x2f */ #define REG_MHL_DP_CTL2 … #define BIT_MHL_DP_CTL2_CLK_BYPASS_EN … #define MSK_MHL_DP_CTL2_DAMP_TERM_SEL … #define MSK_MHL_DP_CTL2_CK_TERM_SEL … #define MSK_MHL_DP_CTL2_DT_TERM_SEL … /* MHL DataPath 4th Ctl, default value: 0x48 */ #define REG_MHL_DP_CTL3 … #define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL … #define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL … /* MHL DataPath 5th Ctl, default value: 0x48 */ #define REG_MHL_DP_CTL4 … #define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL … #define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL … /* MHL DataPath 6th Ctl, default value: 0x3f */ #define REG_MHL_DP_CTL5 … #define BIT_MHL_DP_CTL5_RSEN_EN_OVR … #define BIT_MHL_DP_CTL5_RSEN_EN … #define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL … #define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL … #define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL … /* MHL PLL 1st Ctl, default value: 0x05 */ #define REG_MHL_PLL_CTL0 … #define BIT_MHL_PLL_CTL0_AUD_CLK_EN … #define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME … #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 … #define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO … #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X … #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X … #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X … #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X … #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL … #define BIT_MHL_PLL_CTL0_ZONE_MASK_OE … /* MHL PLL 3rd Ctl, default value: 0x80 */ #define REG_MHL_PLL_CTL2 … #define BIT_MHL_PLL_CTL2_CLKDETECT_EN … #define BIT_MHL_PLL_CTL2_MEAS_FVCO … #define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK … #define MSK_MHL_PLL_CTL2_PLL_LF_SEL … /* MHL CBUS 1st Ctl, default value: 0x12 */ #define REG_MHL_CBUS_CTL0 … #define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE … #define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL … #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 … #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 … #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 … #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 … #define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL … #define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL … #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST … #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK … #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG … #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST … /* MHL CBUS 2nd Ctl, default value: 0x03 */ #define REG_MHL_CBUS_CTL1 … #define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL … #define VAL_MHL_CBUS_CTL1_0888_OHM … #define VAL_MHL_CBUS_CTL1_1115_OHM … #define VAL_MHL_CBUS_CTL1_1378_OHM … /* MHL CoC 1st Ctl, default value: 0xc3 */ #define REG_MHL_COC_CTL0 … #define BIT_MHL_COC_CTL0_COC_BIAS_EN … #define MSK_MHL_COC_CTL0_COC_BIAS_CTL … #define MSK_MHL_COC_CTL0_COC_TERM_CTL … /* MHL CoC 2nd Ctl, default value: 0x87 */ #define REG_MHL_COC_CTL1 … #define BIT_MHL_COC_CTL1_COC_EN … #define MSK_MHL_COC_CTL1_COC_DRV_CTL … /* MHL CoC 4th Ctl, default value: 0x00 */ #define REG_MHL_COC_CTL3 … #define BIT_MHL_COC_CTL3_COC_AECHO_EN … /* MHL CoC 5th Ctl, default value: 0x28 */ #define REG_MHL_COC_CTL4 … #define MSK_MHL_COC_CTL4_COC_IF_CTL … #define MSK_MHL_COC_CTL4_COC_SLEW_CTL … /* MHL CoC 6th Ctl, default value: 0x0d */ #define REG_MHL_COC_CTL5 … /* MHL DoC 1st Ctl, default value: 0x18 */ #define REG_MHL_DOC_CTL0 … #define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN … #define MSK_MHL_DOC_CTL0_DOC_DM_TERM … #define MSK_MHL_DOC_CTL0_DOC_OPMODE … #define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN … /* MHL DataPath 7th Ctl, default value: 0x2a */ #define REG_MHL_DP_CTL6 … #define BIT_MHL_DP_CTL6_DP_TAP2_SGN … #define BIT_MHL_DP_CTL6_DP_TAP2_EN … #define BIT_MHL_DP_CTL6_DP_TAP1_SGN … #define BIT_MHL_DP_CTL6_DP_TAP1_EN … #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN … #define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL … /* MHL DataPath 8th Ctl, default value: 0x06 */ #define REG_MHL_DP_CTL7 … #define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL … #define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL … #define REG_MHL_DP_CTL8 … /* Tx Zone Ctl1, default value: 0x00 */ #define REG_TX_ZONE_CTL1 … #define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE … /* MHL3 Tx Zone Ctl, default value: 0x00 */ #define REG_MHL3_TX_ZONE_CTL … #define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN … #define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE … #define MSK_TX_ZONE_CTL3_TX_ZONE … #define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS … #define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS … #define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS … /* HDCP Polling Control and Status, default value: 0x70 */ #define REG_HDCP2X_POLL_CS … #define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION … #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION … #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION … #define MSK_HDCP2X_POLL_CS_ … #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT … #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN … /* HDCP Interrupt 0, default value: 0x00 */ #define REG_HDCP2X_INTR0 … /* HDCP Interrupt 0 Mask, default value: 0x00 */ #define REG_HDCP2X_INTR0_MASK … /* HDCP General Control 0, default value: 0x02 */ #define REG_HDCP2X_CTRL_0 … #define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN … #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL … #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR … #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE … #define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE … #define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER … #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX … #define BIT_HDCP2X_CTRL_0_HDCP2X_EN … /* HDCP General Control 1, default value: 0x08 */ #define REG_HDCP2X_CTRL_1 … #define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 … #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW … #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR … #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK … #define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW … /* HDCP Misc Control, default value: 0x00 */ #define REG_HDCP2X_MISC_CTRL … #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START … #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START … #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR … #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START … #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD … /* HDCP RPT SMNG K, default value: 0x00 */ #define REG_HDCP2X_RPT_SMNG_K … /* HDCP RPT SMNG In, default value: 0x00 */ #define REG_HDCP2X_RPT_SMNG_IN … /* HDCP Auth Status, default value: 0x00 */ #define REG_HDCP2X_AUTH_STAT … /* HDCP RPT RCVID Out, default value: 0x00 */ #define REG_HDCP2X_RPT_RCVID_OUT … /* HDCP TP1, default value: 0x62 */ #define REG_HDCP2X_TP1 … /* HDCP GP Out 0, default value: 0x00 */ #define REG_HDCP2X_GP_OUT0 … /* HDCP Repeater RCVR ID 0, default value: 0x00 */ #define REG_HDCP2X_RPT_RCVR_ID0 … /* HDCP DDCM Status, default value: 0x00 */ #define REG_HDCP2X_DDCM_STS … #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 … #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 … /* HDMI2MHL3 Control, default value: 0x0a */ #define REG_M3_CTRL … #define BIT_M3_CTRL_H2M_SWRST … #define BIT_M3_CTRL_SW_MHL3_SEL … #define BIT_M3_CTRL_M3AV_EN … #define BIT_M3_CTRL_ENC_TMDS … #define BIT_M3_CTRL_MHL3_MASTER_EN … #define VAL_M3_CTRL_MHL1_2_VALUE … #define VAL_M3_CTRL_MHL3_VALUE … /* HDMI2MHL3 Port0 Control, default value: 0x04 */ #define REG_M3_P0CTRL … #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN … #define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN … #define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN … #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED … #define BIT_M3_P0CTRL_MHL3_P0_PORT_EN … #define REG_M3_POSTM … #define MSK_M3_POSTM_RRP_DECODE … #define MSK_M3_POSTM_MHL3_P0_STM_ID … /* HDMI2MHL3 Scramble Control, default value: 0x41 */ #define REG_M3_SCTRL … #define MSK_M3_SCTRL_MHL3_SR_LENGTH … #define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN … /* HSIC Div Ctl, default value: 0x05 */ #define REG_DIV_CTL_MAIN … #define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN … #define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN … /* MHL Capability 1st Byte, default value: 0x00 */ #define REG_MHL_DEVCAP_0 … /* MHL Interrupt 1st Byte, default value: 0x00 */ #define REG_MHL_INT_0 … /* Device Status 1st byte, default value: 0x00 */ #define REG_MHL_STAT_0 … /* CBUS Scratch Pad 1st Byte, default value: 0x00 */ #define REG_MHL_SCRPAD_0 … /* MHL Extended Capability 1st Byte, default value: 0x00 */ #define REG_MHL_EXTDEVCAP_0 … /* Device Extended Status 1st byte, default value: 0x00 */ #define REG_MHL_EXTSTAT_0 … /* TPI DTD Byte2, default value: 0x00 */ #define REG_TPI_DTD_B2 … #define VAL_TPI_QUAN_RANGE_LIMITED … #define VAL_TPI_QUAN_RANGE_FULL … #define VAL_TPI_FORMAT_RGB … #define VAL_TPI_FORMAT_YCBCR444 … #define VAL_TPI_FORMAT_YCBCR422 … #define VAL_TPI_FORMAT_INTERNAL_RGB … #define VAL_TPI_FORMAT(_fmt, _qr) … /* Input Format, default value: 0x00 */ #define REG_TPI_INPUT … #define BIT_TPI_INPUT_EXTENDEDBITMODE … #define BIT_TPI_INPUT_ENDITHER … #define MSK_TPI_INPUT_INPUT_QUAN_RANGE … #define MSK_TPI_INPUT_INPUT_FORMAT … /* Output Format, default value: 0x00 */ #define REG_TPI_OUTPUT … #define BIT_TPI_OUTPUT_CSCMODE709 … #define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE … #define MSK_TPI_OUTPUT_OUTPUT_FORMAT … /* TPI AVI Check Sum, default value: 0x00 */ #define REG_TPI_AVI_CHSUM … /* TPI System Control, default value: 0x00 */ #define REG_TPI_SC … #define BIT_TPI_SC_TPI_UPDATE_FLG … #define BIT_TPI_SC_TPI_REAUTH_CTL … #define BIT_TPI_SC_TPI_OUTPUT_MODE_1 … #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN … #define BIT_TPI_SC_TPI_AV_MUTE … #define BIT_TPI_SC_DDC_GPU_REQUEST … #define BIT_TPI_SC_DDC_TPI_SW … #define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI … /* TPI COPP Query Data, default value: 0x00 */ #define REG_TPI_COPP_DATA1 … #define BIT_TPI_COPP_DATA1_COPP_GPROT … #define BIT_TPI_COPP_DATA1_COPP_LPROT … #define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS … #define VAL_TPI_COPP_LINK_STATUS_NORMAL … #define VAL_TPI_COPP_LINK_STATUS_LINK_LOST … #define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ … #define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED … #define BIT_TPI_COPP_DATA1_COPP_HDCP_REP … #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 … #define BIT_TPI_COPP_DATA1_COPP_PROTYPE … #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 … /* TPI COPP Control Data, default value: 0x00 */ #define REG_TPI_COPP_DATA2 … #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION … #define BIT_TPI_COPP_DATA2_KSV_FORWARD … #define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN … #define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK … #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD … #define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL … /* TPI Interrupt Enable, default value: 0x00 */ #define REG_TPI_INTR_EN … /* TPI Interrupt Status Low Byte, default value: 0x00 */ #define REG_TPI_INTR_ST0 … #define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT … #define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT … #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT … #define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT … #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT … #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT … #define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT … /* TPI DS BCAPS Status, default value: 0x00 */ #define REG_TPI_DS_BCAPS … /* TPI BStatus1, default value: 0x00 */ #define REG_TPI_BSTATUS1 … #define BIT_TPI_BSTATUS1_DS_DEV_EXCEED … #define MSK_TPI_BSTATUS1_DS_DEV_CNT … /* TPI BStatus2, default value: 0x10 */ #define REG_TPI_BSTATUS2 … #define MSK_TPI_BSTATUS2_DS_BSTATUS … #define BIT_TPI_BSTATUS2_DS_HDMI_MODE … #define BIT_TPI_BSTATUS2_DS_CASC_EXCEED … #define MSK_TPI_BSTATUS2_DS_DEPTH … /* TPI HW Optimization Control #3, default value: 0x00 */ #define REG_TPI_HW_OPT3 … #define BIT_TPI_HW_OPT3_DDC_DEBUG … #define BIT_TPI_HW_OPT3_RI_CHECK_SKIP … #define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE … #define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL … /* TPI Info Frame Select, default value: 0x00 */ #define REG_TPI_INFO_FSEL … #define BIT_TPI_INFO_FSEL_EN … #define BIT_TPI_INFO_FSEL_RPT … #define BIT_TPI_INFO_FSEL_READ_FLAG … #define MSK_TPI_INFO_FSEL_PKT … #define VAL_TPI_INFO_FSEL_AVI … #define VAL_TPI_INFO_FSEL_SPD … #define VAL_TPI_INFO_FSEL_AUD … #define VAL_TPI_INFO_FSEL_MPG … #define VAL_TPI_INFO_FSEL_GEN … #define VAL_TPI_INFO_FSEL_GEN2 … #define VAL_TPI_INFO_FSEL_VSI … /* TPI Info Byte #0, default value: 0x00 */ #define REG_TPI_INFO_B0 … /* CoC Status, default value: 0x00 */ #define REG_COC_STAT_0 … #define BIT_COC_STAT_0_PLL_LOCKED … #define MSK_COC_STAT_0_FSM_STATE … #define REG_COC_STAT_1 … #define REG_COC_STAT_2 … #define REG_COC_STAT_3 … #define REG_COC_STAT_4 … #define REG_COC_STAT_5 … /* CoC 1st Ctl, default value: 0x40 */ #define REG_COC_CTL0 … /* CoC 2nd Ctl, default value: 0x0a */ #define REG_COC_CTL1 … #define MSK_COC_CTL1_COC_CTRL1_7_6 … #define MSK_COC_CTL1_COC_CTRL1_5_0 … /* CoC 3rd Ctl, default value: 0x14 */ #define REG_COC_CTL2 … #define MSK_COC_CTL2_COC_CTRL2_7_6 … #define MSK_COC_CTL2_COC_CTRL2_5_0 … /* CoC 4th Ctl, default value: 0x40 */ #define REG_COC_CTL3 … #define BIT_COC_CTL3_COC_CTRL3_7 … #define MSK_COC_CTL3_COC_CTRL3_6_0 … /* CoC 7th Ctl, default value: 0x00 */ #define REG_COC_CTL6 … #define BIT_COC_CTL6_COC_CTRL6_7 … #define BIT_COC_CTL6_COC_CTRL6_6 … #define MSK_COC_CTL6_COC_CTRL6_5_0 … /* CoC 8th Ctl, default value: 0x06 */ #define REG_COC_CTL7 … #define BIT_COC_CTL7_COC_CTRL7_7 … #define BIT_COC_CTL7_COC_CTRL7_6 … #define BIT_COC_CTL7_COC_CTRL7_5 … #define MSK_COC_CTL7_COC_CTRL7_4_3 … #define MSK_COC_CTL7_COC_CTRL7_2_0 … /* CoC 10th Ctl, default value: 0x00 */ #define REG_COC_CTL9 … /* CoC 11th Ctl, default value: 0x00 */ #define REG_COC_CTLA … /* CoC 12th Ctl, default value: 0x00 */ #define REG_COC_CTLB … /* CoC 13th Ctl, default value: 0x0f */ #define REG_COC_CTLC … /* CoC 14th Ctl, default value: 0x0a */ #define REG_COC_CTLD … #define BIT_COC_CTLD_COC_CTRLD_7 … #define MSK_COC_CTLD_COC_CTRLD_6_0 … /* CoC 15th Ctl, default value: 0x0a */ #define REG_COC_CTLE … #define BIT_COC_CTLE_COC_CTRLE_7 … #define MSK_COC_CTLE_COC_CTRLE_6_0 … /* CoC 16th Ctl, default value: 0x00 */ #define REG_COC_CTLF … #define MSK_COC_CTLF_COC_CTRLF_7_3 … #define MSK_COC_CTLF_COC_CTRLF_2_0 … /* CoC 18th Ctl, default value: 0x32 */ #define REG_COC_CTL11 … #define MSK_COC_CTL11_COC_CTRL11_7_4 … #define MSK_COC_CTL11_COC_CTRL11_3_0 … /* CoC 21st Ctl, default value: 0x00 */ #define REG_COC_CTL14 … #define MSK_COC_CTL14_COC_CTRL14_7_4 … #define MSK_COC_CTL14_COC_CTRL14_3_0 … /* CoC 22nd Ctl, default value: 0x00 */ #define REG_COC_CTL15 … #define BIT_COC_CTL15_COC_CTRL15_7 … #define MSK_COC_CTL15_COC_CTRL15_6_4 … #define MSK_COC_CTL15_COC_CTRL15_3_0 … /* CoC Interrupt, default value: 0x00 */ #define REG_COC_INTR … /* CoC Interrupt Mask, default value: 0x00 */ #define REG_COC_INTR_MASK … #define BIT_COC_PLL_LOCK_STATUS_CHANGE … #define BIT_COC_CALIBRATION_DONE … /* CoC Misc Ctl, default value: 0x00 */ #define REG_COC_MISC_CTL0 … #define BIT_COC_MISC_CTL0_FSM_MON … /* CoC 24th Ctl, default value: 0x00 */ #define REG_COC_CTL17 … #define MSK_COC_CTL17_COC_CTRL17_7_4 … #define MSK_COC_CTL17_COC_CTRL17_3_0 … /* CoC 25th Ctl, default value: 0x00 */ #define REG_COC_CTL18 … #define MSK_COC_CTL18_COC_CTRL18_7_4 … #define MSK_COC_CTL18_COC_CTRL18_3_0 … /* CoC 26th Ctl, default value: 0x00 */ #define REG_COC_CTL19 … #define MSK_COC_CTL19_COC_CTRL19_7_4 … #define MSK_COC_CTL19_COC_CTRL19_3_0 … /* CoC 27th Ctl, default value: 0x00 */ #define REG_COC_CTL1A … #define MSK_COC_CTL1A_COC_CTRL1A_7_2 … #define MSK_COC_CTL1A_COC_CTRL1A_1_0 … /* DoC 9th Status, default value: 0x00 */ #define REG_DOC_STAT_8 … /* DoC 10th Status, default value: 0x00 */ #define REG_DOC_STAT_9 … /* DoC 5th CFG, default value: 0x00 */ #define REG_DOC_CFG4 … #define MSK_DOC_CFG4_DBG_STATE_DOC_FSM … /* DoC 1st Ctl, default value: 0x40 */ #define REG_DOC_CTL0 … /* DoC 7th Ctl, default value: 0x00 */ #define REG_DOC_CTL6 … #define BIT_DOC_CTL6_DOC_CTRL6_7 … #define BIT_DOC_CTL6_DOC_CTRL6_6 … #define MSK_DOC_CTL6_DOC_CTRL6_5_4 … #define MSK_DOC_CTL6_DOC_CTRL6_3_0 … /* DoC 8th Ctl, default value: 0x00 */ #define REG_DOC_CTL7 … #define BIT_DOC_CTL7_DOC_CTRL7_7 … #define BIT_DOC_CTL7_DOC_CTRL7_6 … #define BIT_DOC_CTL7_DOC_CTRL7_5 … #define MSK_DOC_CTL7_DOC_CTRL7_4_3 … #define MSK_DOC_CTL7_DOC_CTRL7_2_0 … /* DoC 9th Ctl, default value: 0x00 */ #define REG_DOC_CTL8 … #define BIT_DOC_CTL8_DOC_CTRL8_7 … #define MSK_DOC_CTL8_DOC_CTRL8_6_4 … #define MSK_DOC_CTL8_DOC_CTRL8_3_2 … #define MSK_DOC_CTL8_DOC_CTRL8_1_0 … /* DoC 10th Ctl, default value: 0x00 */ #define REG_DOC_CTL9 … /* DoC 11th Ctl, default value: 0x00 */ #define REG_DOC_CTLA … /* DoC 15th Ctl, default value: 0x00 */ #define REG_DOC_CTLE … #define BIT_DOC_CTLE_DOC_CTRLE_7 … #define BIT_DOC_CTLE_DOC_CTRLE_6 … #define MSK_DOC_CTLE_DOC_CTRLE_5_4 … #define MSK_DOC_CTLE_DOC_CTRLE_3_0 … /* Interrupt Mask 1st, default value: 0x00 */ #define REG_MHL_INT_0_MASK … /* Interrupt Mask 2nd, default value: 0x00 */ #define REG_MHL_INT_1_MASK … /* Interrupt Mask 3rd, default value: 0x00 */ #define REG_MHL_INT_2_MASK … /* Interrupt Mask 4th, default value: 0x00 */ #define REG_MHL_INT_3_MASK … /* MDT Receive Time Out, default value: 0x00 */ #define REG_MDT_RCV_TIMEOUT … /* MDT Transmit Time Out, default value: 0x00 */ #define REG_MDT_XMIT_TIMEOUT … /* MDT Receive Control, default value: 0x00 */ #define REG_MDT_RCV_CTRL … #define BIT_MDT_RCV_CTRL_MDT_RCV_EN … #define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN … #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN … #define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN … #define BIT_MDT_RCV_CTRL_MDT_DISABLE … #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL … #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR … /* MDT Receive Read Port, default value: 0x00 */ #define REG_MDT_RCV_READ_PORT … /* MDT Transmit Control, default value: 0x70 */ #define REG_MDT_XMIT_CTRL … #define BIT_MDT_XMIT_CTRL_EN … #define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN … #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN … #define BIT_MDT_XMIT_CTRL_FIXED_AID … #define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN … #define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT … #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL … #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR … /* MDT Receive WRITE Port, default value: 0x00 */ #define REG_MDT_XMIT_WRITE_PORT … /* MDT RFIFO Status, default value: 0x00 */ #define REG_MDT_RFIFO_STAT … #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT … #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT … /* MDT XFIFO Status, default value: 0x80 */ #define REG_MDT_XFIFO_STAT … #define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL … #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN … #define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN … /* MDT Interrupt 0, default value: 0x0c */ #define REG_MDT_INT_0 … #define BIT_MDT_RFIFO_DATA_RDY … #define BIT_MDT_IDLE_AFTER_HAWB_DISABLE … #define BIT_MDT_XFIFO_EMPTY … /* MDT Interrupt 0 Mask, default value: 0x00 */ #define REG_MDT_INT_0_MASK … /* MDT Interrupt 1, default value: 0x00 */ #define REG_MDT_INT_1 … #define BIT_MDT_RCV_TIMEOUT … #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD … #define BIT_MDT_RCV_SM_ERROR … #define BIT_MDT_XMIT_TIMEOUT … #define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD … #define BIT_MDT_XMIT_SM_ERROR … /* MDT Interrupt 1 Mask, default value: 0x00 */ #define REG_MDT_INT_1_MASK … /* CBUS Vendor ID, default value: 0x01 */ #define REG_CBUS_VENDOR_ID … /* CBUS Connection Status, default value: 0x00 */ #define REG_CBUS_STATUS … #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT … #define BIT_CBUS_STATUS_MSC_HB_SUCCESS … #define BIT_CBUS_STATUS_CBUS_HPD … #define BIT_CBUS_STATUS_MHL_MODE … #define BIT_CBUS_STATUS_CBUS_CONNECTED … /* CBUS Interrupt 1st, default value: 0x00 */ #define REG_CBUS_INT_0 … #define BIT_CBUS_MSC_MT_DONE_NACK … #define BIT_CBUS_MSC_MR_SET_INT … #define BIT_CBUS_MSC_MR_WRITE_BURST … #define BIT_CBUS_MSC_MR_MSC_MSG … #define BIT_CBUS_MSC_MR_WRITE_STAT … #define BIT_CBUS_HPD_CHG … #define BIT_CBUS_MSC_MT_DONE … #define BIT_CBUS_CNX_CHG … /* CBUS Interrupt Mask 1st, default value: 0x00 */ #define REG_CBUS_INT_0_MASK … /* CBUS Interrupt 2nd, default value: 0x00 */ #define REG_CBUS_INT_1 … #define BIT_CBUS_CMD_ABORT … #define BIT_CBUS_MSC_ABORT_RCVD … #define BIT_CBUS_DDC_ABORT … #define BIT_CBUS_CEC_ABORT … /* CBUS Interrupt Mask 2nd, default value: 0x00 */ #define REG_CBUS_INT_1_MASK … /* CBUS DDC Abort Interrupt, default value: 0x00 */ #define REG_DDC_ABORT_INT … /* CBUS DDC Abort Interrupt Mask, default value: 0x00 */ #define REG_DDC_ABORT_INT_MASK … /* CBUS MSC Requester Abort Interrupt, default value: 0x00 */ #define REG_MSC_MT_ABORT_INT … /* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */ #define REG_MSC_MT_ABORT_INT_MASK … /* CBUS MSC Responder Abort Interrupt, default value: 0x00 */ #define REG_MSC_MR_ABORT_INT … /* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */ #define REG_MSC_MR_ABORT_INT_MASK … /* CBUS RX DISCOVERY interrupt, default value: 0x00 */ #define REG_CBUS_RX_DISC_INT0 … /* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */ #define REG_CBUS_RX_DISC_INT0_MASK … /* CBUS_Link_Layer Control #8, default value: 0x00 */ #define REG_CBUS_LINK_CTRL_8 … /* MDT State Machine Status, default value: 0x00 */ #define REG_MDT_SM_STAT … #define MSK_MDT_SM_STAT_MDT_RCV_STATE … #define MSK_MDT_SM_STAT_MDT_XMIT_STATE … /* CBUS MSC command trigger, default value: 0x00 */ #define REG_MSC_COMMAND_START … #define BIT_MSC_COMMAND_START_DEBUG … #define BIT_MSC_COMMAND_START_WRITE_BURST … #define BIT_MSC_COMMAND_START_WRITE_STAT … #define BIT_MSC_COMMAND_START_READ_DEVCAP … #define BIT_MSC_COMMAND_START_MSC_MSG … #define BIT_MSC_COMMAND_START_PEER … /* CBUS MSC Command/Offset, default value: 0x00 */ #define REG_MSC_CMD_OR_OFFSET … /* CBUS MSC Transmit Data */ #define REG_MSC_1ST_TRANSMIT_DATA … #define REG_MSC_2ND_TRANSMIT_DATA … /* CBUS MSC Requester Received Data */ #define REG_MSC_MT_RCVD_DATA0 … #define REG_MSC_MT_RCVD_DATA1 … /* CBUS MSC Responder MSC_MSG Received Data */ #define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA … #define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA … /* CBUS MSC Heartbeat Control, default value: 0x27 */ #define REG_MSC_HEARTBEAT_CTRL … #define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN … #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT … #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB … /* CBUS MSC Compatibility Control, default value: 0x02 */ #define REG_CBUS_MSC_COMPAT_CTRL … #define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN … #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS … #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS … #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE … #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE … /* CBUS3 Converter Control, default value: 0x24 */ #define REG_CBUS3_CNVT … #define MSK_CBUS3_CNVT_CBUS3_RETRYLMT … #define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL … #define BIT_CBUS3_CNVT_TEARCBUS_EN … #define BIT_CBUS3_CNVT_CBUS3CNVT_EN … /* Discovery Control1, default value: 0x24 */ #define REG_DISC_CTRL1 … #define BIT_DISC_CTRL1_CBUS_INTR_EN … #define BIT_DISC_CTRL1_HB_ONLY … #define MSK_DISC_CTRL1_DISC_ATT … #define MSK_DISC_CTRL1_DISC_CYC … #define BIT_DISC_CTRL1_DISC_EN … #define VAL_PUP_OFF … #define VAL_PUP_20K … #define VAL_PUP_5K … /* Discovery Control4, default value: 0x80 */ #define REG_DISC_CTRL4 … #define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL … #define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL … #define VAL_DISC_CTRL4(pup_disc, pup_idle) … /* Discovery Control5, default value: 0x03 */ #define REG_DISC_CTRL5 … #define BIT_DISC_CTRL5_DSM_OVRIDE … #define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL … /* Discovery Control8, default value: 0x81 */ #define REG_DISC_CTRL8 … #define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS … #define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN … /* Discovery Control9, default value: 0x54 */ #define REG_DISC_CTRL9 … #define BIT_DISC_CTRL9_MHL3_RSEN_BYP … #define BIT_DISC_CTRL9_MHL3DISC_EN … #define BIT_DISC_CTRL9_WAKE_DRVFLT … #define BIT_DISC_CTRL9_NOMHL_EST … #define BIT_DISC_CTRL9_DISC_PULSE_PROCEED … #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS … #define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC … /* Discovery Status1, default value: 0x00 */ #define REG_DISC_STAT1 … #define BIT_DISC_STAT1_PSM_OVRIDE … #define MSK_DISC_STAT1_DISC_SM … /* Discovery Status2, default value: 0x00 */ #define REG_DISC_STAT2 … #define BIT_DISC_STAT2_CBUS_OE_POL … #define BIT_DISC_STAT2_CBUS_SATUS … #define BIT_DISC_STAT2_RSEN … #define MSK_DISC_STAT2_MHL_VRSN … #define VAL_DISC_STAT2_DEFAULT … #define VAL_DISC_STAT2_MHL1_2 … #define VAL_DISC_STAT2_MHL3 … #define VAL_DISC_STAT2_RESERVED … #define MSK_DISC_STAT2_RGND … #define VAL_RGND_OPEN … #define VAL_RGND_2K … #define VAL_RGND_1K … #define VAL_RGND_SHORT … /* Interrupt CBUS_reg1 INTR0, default value: 0x00 */ #define REG_CBUS_DISC_INTR0 … #define BIT_RGND_READY_INT … #define BIT_CBUS_MHL12_DISCON_INT … #define BIT_CBUS_MHL3_DISCON_INT … #define BIT_NOT_MHL_EST_INT … #define BIT_MHL_EST_INT … #define BIT_MHL3_EST_INT … #define VAL_CBUS_MHL_DISCON … /* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */ #define REG_CBUS_DISC_INTR0_MASK … #endif /* __SIL_SII8620_H__ */
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