// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <[email protected]> */ #include <linux/clk.h> #include <linux/device.h> #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/kernel.h> #include <linux/math64.h> #include <linux/media-bus-format.h> #include <linux/minmax.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> #include <linux/units.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_drv.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_of.h> #include <drm/drm_panel.h> #include <video/mipi_display.h> #include <video/videomode.h> /* Global (16-bit addressable) */ #define TC358768_CHIPID … #define TC358768_SYSCTL … #define TC358768_CONFCTL … #define TC358768_VSDLY … #define TC358768_DATAFMT … #define TC358768_GPIOEN … #define TC358768_GPIODIR … #define TC358768_GPIOIN … #define TC358768_GPIOOUT … #define TC358768_PLLCTL0 … #define TC358768_PLLCTL1 … #define TC358768_CMDBYTE … #define TC358768_PP_MISC … #define TC358768_DSITX_DT … #define TC358768_FIFOSTATUS … /* Debug (16-bit addressable) */ #define TC358768_VBUFCTRL … #define TC358768_DBG_WIDTH … #define TC358768_DBG_VBLANK … #define TC358768_DBG_DATA … /* TX PHY (32-bit addressable) */ #define TC358768_CLW_DPHYCONTTX … #define TC358768_D0W_DPHYCONTTX … #define TC358768_D1W_DPHYCONTTX … #define TC358768_D2W_DPHYCONTTX … #define TC358768_D3W_DPHYCONTTX … #define TC358768_CLW_CNTRL … #define TC358768_D0W_CNTRL … #define TC358768_D1W_CNTRL … #define TC358768_D2W_CNTRL … #define TC358768_D3W_CNTRL … /* TX PPI (32-bit addressable) */ #define TC358768_STARTCNTRL … #define TC358768_DSITXSTATUS … #define TC358768_LINEINITCNT … #define TC358768_LPTXTIMECNT … #define TC358768_TCLK_HEADERCNT … #define TC358768_TCLK_TRAILCNT … #define TC358768_THS_HEADERCNT … #define TC358768_TWAKEUP … #define TC358768_TCLK_POSTCNT … #define TC358768_THS_TRAILCNT … #define TC358768_HSTXVREGCNT … #define TC358768_HSTXVREGEN … #define TC358768_TXOPTIONCNTRL … #define TC358768_BTACNTRL1 … /* TX CTRL (32-bit addressable) */ #define TC358768_DSI_CONTROL … #define TC358768_DSI_STATUS … #define TC358768_DSI_INT … #define TC358768_DSI_INT_ENA … #define TC358768_DSICMD_RDFIFO … #define TC358768_DSI_ACKERR … #define TC358768_DSI_ACKERR_INTENA … #define TC358768_DSI_ACKERR_HALT … #define TC358768_DSI_RXERR … #define TC358768_DSI_RXERR_INTENA … #define TC358768_DSI_RXERR_HALT … #define TC358768_DSI_ERR … #define TC358768_DSI_ERR_INTENA … #define TC358768_DSI_ERR_HALT … #define TC358768_DSI_CONFW … #define TC358768_DSI_LPCMD … #define TC358768_DSI_RESET … #define TC358768_DSI_INT_CLR … #define TC358768_DSI_START … /* DSITX CTRL (16-bit addressable) */ #define TC358768_DSICMD_TX … #define TC358768_DSICMD_TYPE … #define TC358768_DSICMD_WC … #define TC358768_DSICMD_WD0 … #define TC358768_DSICMD_WD1 … #define TC358768_DSICMD_WD2 … #define TC358768_DSICMD_WD3 … #define TC358768_DSI_EVENT … #define TC358768_DSI_VSW … #define TC358768_DSI_VBPR … #define TC358768_DSI_VACT … #define TC358768_DSI_HSW … #define TC358768_DSI_HBPR … #define TC358768_DSI_HACT … /* TC358768_DSI_CONTROL (0x040C) register */ #define TC358768_DSI_CONTROL_DIS_MODE … #define TC358768_DSI_CONTROL_TXMD … #define TC358768_DSI_CONTROL_HSCKMD … #define TC358768_DSI_CONTROL_EOTDIS … /* TC358768_DSI_CONFW (0x0500) register */ #define TC358768_DSI_CONFW_MODE_SET … #define TC358768_DSI_CONFW_MODE_CLR … #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL … static const char * const tc358768_supplies[] = …; struct tc358768_dsi_output { … }; struct tc358768_priv { … }; static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host *host) { … } static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge *bridge) { … } static int tc358768_clear_error(struct tc358768_priv *priv) { … } static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) { … } static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) { … } static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, u32 val) { … } static int tc358768_sw_reset(struct tc358768_priv *priv) { … } static void tc358768_hw_enable(struct tc358768_priv *priv) { … } static void tc358768_hw_disable(struct tc358768_priv *priv) { … } static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) { … } static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) { … } static int tc358768_calc_pll(struct tc358768_priv *priv, const struct drm_display_mode *mode, bool verify_only) { … } static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) { … } static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) { … } static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg) { … } static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = …; static int tc358768_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { … } static enum drm_mode_status tc358768_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { … } static void tc358768_bridge_disable(struct drm_bridge *bridge) { … } static void tc358768_bridge_post_disable(struct drm_bridge *bridge) { … } static int tc358768_setup_pll(struct tc358768_priv *priv, const struct drm_display_mode *mode) { … } static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { … } static u32 tc358768_ps_to_ns(u32 ps) { … } static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) { … } /* Convert value in DPI pixel clock units to DSI byte count */ static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) { … } static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) { … } static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) { … } static void tc358768_bridge_enable(struct drm_bridge *bridge) { … } #define MAX_INPUT_SEL_FORMATS … static u32 * tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state, u32 output_fmt, unsigned int *num_input_fmts) { … } static bool tc358768_mode_fixup(struct drm_bridge *bridge, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { … } static const struct drm_bridge_funcs tc358768_bridge_funcs = …; static const struct drm_bridge_timings default_tc358768_timings = …; static bool tc358768_is_reserved_reg(unsigned int reg) { … } static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) { … } static bool tc358768_readable_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config tc358768_regmap_config = …; static const struct i2c_device_id tc358768_i2c_ids[] = …; MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); static const struct of_device_id tc358768_of_ids[] = …; MODULE_DEVICE_TABLE(of, tc358768_of_ids); static int tc358768_get_regulators(struct tc358768_priv *priv) { … } static int tc358768_i2c_probe(struct i2c_client *client) { … } static void tc358768_i2c_remove(struct i2c_client *client) { … } static struct i2c_driver tc358768_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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