/* SPDX-License-Identifier: GPL-2.0+ */ /* * NWL MIPI DSI host driver * * Copyright (C) 2017 NXP * Copyright (C) 2019 Purism SPC */ #ifndef __NWL_DSI_H__ #define __NWL_DSI_H__ /* DSI HOST registers */ #define NWL_DSI_CFG_NUM_LANES … #define NWL_DSI_CFG_NONCONTINUOUS_CLK … #define NWL_DSI_CFG_T_PRE … #define NWL_DSI_CFG_T_POST … #define NWL_DSI_CFG_TX_GAP … #define NWL_DSI_CFG_AUTOINSERT_EOTP … #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP … #define NWL_DSI_CFG_HTX_TO_COUNT … #define NWL_DSI_CFG_LRX_H_TO_COUNT … #define NWL_DSI_CFG_BTA_H_TO_COUNT … #define NWL_DSI_CFG_TWAKEUP … #define NWL_DSI_CFG_STATUS_OUT … #define NWL_DSI_RX_ERROR_STATUS … /* DSI DPI registers */ #define NWL_DSI_PIXEL_PAYLOAD_SIZE … #define NWL_DSI_PIXEL_FIFO_SEND_LEVEL … #define NWL_DSI_INTERFACE_COLOR_CODING … #define NWL_DSI_PIXEL_FORMAT … #define NWL_DSI_VSYNC_POLARITY … #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW … #define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH … #define NWL_DSI_HSYNC_POLARITY … #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW … #define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH … #define NWL_DSI_VIDEO_MODE … #define NWL_DSI_HFP … #define NWL_DSI_HBP … #define NWL_DSI_HSA … #define NWL_DSI_ENABLE_MULT_PKTS … #define NWL_DSI_VBP … #define NWL_DSI_VFP … #define NWL_DSI_BLLP_MODE … #define NWL_DSI_USE_NULL_PKT_BLLP … #define NWL_DSI_VACTIVE … #define NWL_DSI_VC … /* DSI APB PKT control */ #define NWL_DSI_TX_PAYLOAD … #define NWL_DSI_PKT_CONTROL … #define NWL_DSI_SEND_PACKET … #define NWL_DSI_PKT_STATUS … #define NWL_DSI_PKT_FIFO_WR_LEVEL … #define NWL_DSI_PKT_FIFO_RD_LEVEL … #define NWL_DSI_RX_PAYLOAD … #define NWL_DSI_RX_PKT_HEADER … /* DSI IRQ handling */ #define NWL_DSI_IRQ_STATUS … #define NWL_DSI_SM_NOT_IDLE … #define NWL_DSI_TX_PKT_DONE … #define NWL_DSI_DPHY_DIRECTION … #define NWL_DSI_TX_FIFO_OVFLW … #define NWL_DSI_TX_FIFO_UDFLW … #define NWL_DSI_RX_FIFO_OVFLW … #define NWL_DSI_RX_FIFO_UDFLW … #define NWL_DSI_RX_PKT_HDR_RCVD … #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD … #define NWL_DSI_BTA_TIMEOUT … #define NWL_DSI_LP_RX_TIMEOUT … #define NWL_DSI_HS_TX_TIMEOUT … #define NWL_DSI_IRQ_STATUS2 … #define NWL_DSI_SINGLE_BIT_ECC_ERR … #define NWL_DSI_MULTI_BIT_ECC_ERR … #define NWL_DSI_CRC_ERR … #define NWL_DSI_IRQ_MASK … #define NWL_DSI_SM_NOT_IDLE_MASK … #define NWL_DSI_TX_PKT_DONE_MASK … #define NWL_DSI_DPHY_DIRECTION_MASK … #define NWL_DSI_TX_FIFO_OVFLW_MASK … #define NWL_DSI_TX_FIFO_UDFLW_MASK … #define NWL_DSI_RX_FIFO_OVFLW_MASK … #define NWL_DSI_RX_FIFO_UDFLW_MASK … #define NWL_DSI_RX_PKT_HDR_RCVD_MASK … #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK … #define NWL_DSI_BTA_TIMEOUT_MASK … #define NWL_DSI_LP_RX_TIMEOUT_MASK … #define NWL_DSI_HS_TX_TIMEOUT_MASK … #define NWL_DSI_IRQ_MASK2 … #define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK … #define NWL_DSI_MULTI_BIT_ECC_ERR_MASK … #define NWL_DSI_CRC_ERR_MASK … /* * PKT_CONTROL format: * [15: 0] - word count * [17:16] - virtual channel * [23:18] - data type * [24] - LP or HS select (0 - LP, 1 - HS) * [25] - perform BTA after packet is sent * [26] - perform BTA only, no packet tx */ #define NWL_DSI_WC(x) … #define NWL_DSI_TX_VC(x) … #define NWL_DSI_TX_DT(x) … #define NWL_DSI_HS_SEL(x) … #define NWL_DSI_BTA_TX(x) … #define NWL_DSI_BTA_NO_TX(x) … /* * RX_PKT_HEADER format: * [15: 0] - word count * [21:16] - data type * [23:22] - virtual channel */ #define NWL_DSI_RX_DT(x) … #define NWL_DSI_RX_VC(x) … /* DSI Video mode */ #define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES … #define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS … #define NWL_DSI_VM_BURST_MODE … /* * DPI color coding */ #define NWL_DSI_DPI_16_BIT_565_PACKED … #define NWL_DSI_DPI_16_BIT_565_ALIGNED … #define NWL_DSI_DPI_16_BIT_565_SHIFTED … #define NWL_DSI_DPI_18_BIT_PACKED … #define NWL_DSI_DPI_18_BIT_ALIGNED … #define NWL_DSI_DPI_24_BIT … /* * DPI Pixel format */ #define NWL_DSI_PIXEL_FORMAT_16 … #define NWL_DSI_PIXEL_FORMAT_18 … #define NWL_DSI_PIXEL_FORMAT_18L … #define NWL_DSI_PIXEL_FORMAT_24 … #endif /* __NWL_DSI_H__ */
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