/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Hisilicon Hibmc SoC drm driver * * Based on the bochs drm driver. * * Copyright (c) 2016 Huawei Limited. * * Author: * Rongrong Zou <[email protected]> * Rongrong Zou <[email protected]> * Jianhua Li <[email protected]> */ #ifndef HIBMC_DRM_HW_H #define HIBMC_DRM_HW_H /* register definition */ #define HIBMC_MISC_CTRL … #define HIBMC_MSCCTL_LOCALMEM_RESET(x) … #define HIBMC_MSCCTL_LOCALMEM_RESET_MASK … #define HIBMC_CURRENT_GATE … #define HIBMC_CURR_GATE_DISPLAY(x) … #define HIBMC_CURR_GATE_DISPLAY_MASK … #define HIBMC_CURR_GATE_LOCALMEM(x) … #define HIBMC_CURR_GATE_LOCALMEM_MASK … #define HIBMC_MODE0_GATE … #define HIBMC_MODE1_GATE … #define HIBMC_POWER_MODE_CTRL … #define HIBMC_PW_MODE_CTL_OSC_INPUT(x) … #define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK … #define HIBMC_PW_MODE_CTL_MODE(x) … #define HIBMC_PW_MODE_CTL_MODE_MASK … #define HIBMC_PW_MODE_CTL_MODE_SHIFT … #define HIBMC_PW_MODE_CTL_MODE_MODE0 … #define HIBMC_PW_MODE_CTL_MODE_MODE1 … #define HIBMC_PW_MODE_CTL_MODE_SLEEP … #define HIBMC_PANEL_PLL_CTRL … #define HIBMC_CRT_PLL_CTRL … #define HIBMC_PLL_CTRL_BYPASS(x) … #define HIBMC_PLL_CTRL_BYPASS_MASK … #define HIBMC_PLL_CTRL_POWER(x) … #define HIBMC_PLL_CTRL_POWER_MASK … #define HIBMC_PLL_CTRL_INPUT(x) … #define HIBMC_PLL_CTRL_INPUT_MASK … #define HIBMC_PLL_CTRL_POD(x) … #define HIBMC_PLL_CTRL_POD_MASK … #define HIBMC_PLL_CTRL_OD(x) … #define HIBMC_PLL_CTRL_OD_MASK … #define HIBMC_PLL_CTRL_N(x) … #define HIBMC_PLL_CTRL_N_MASK … #define HIBMC_PLL_CTRL_M(x) … #define HIBMC_PLL_CTRL_M_MASK … #define HIBMC_CRT_DISP_CTL … #define HIBMC_CRT_DISP_CTL_DPMS(x) … #define HIBMC_CRT_DISP_CTL_DPMS_MASK … #define HIBMC_CRT_DPMS_ON … #define HIBMC_CRT_DPMS_OFF … #define HIBMC_CRT_DISP_CTL_CRTSELECT(x) … #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK … #define HIBMC_CRTSELECT_CRT … #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) … #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK … #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) … #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK … #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) … #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK … #define HIBMC_CRT_DISP_CTL_TIMING(x) … #define HIBMC_CRT_DISP_CTL_TIMING_MASK … #define HIBMC_CTL_DISP_CTL_GAMMA(x) … #define HIBMC_CTL_DISP_CTL_GAMMA_MASK … #define HIBMC_CRT_DISP_CTL_PLANE(x) … #define HIBMC_CRT_DISP_CTL_PLANE_MASK … #define HIBMC_CRT_DISP_CTL_FORMAT(x) … #define HIBMC_CRT_DISP_CTL_FORMAT_MASK … #define HIBMC_CRT_FB_ADDRESS … #define HIBMC_CRT_FB_WIDTH … #define HIBMC_CRT_FB_WIDTH_WIDTH(x) … #define HIBMC_CRT_FB_WIDTH_WIDTH_MASK … #define HIBMC_CRT_FB_WIDTH_OFFS(x) … #define HIBMC_CRT_FB_WIDTH_OFFS_MASK … #define HIBMC_CRT_HORZ_TOTAL … #define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) … #define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK … #define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) … #define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK … #define HIBMC_CRT_HORZ_SYNC … #define HIBMC_CRT_HORZ_SYNC_WIDTH(x) … #define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK … #define HIBMC_CRT_HORZ_SYNC_START(x) … #define HIBMC_CRT_HORZ_SYNC_START_MASK … #define HIBMC_CRT_VERT_TOTAL … #define HIBMC_CRT_VERT_TOTAL_TOTAL(x) … #define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK … #define HIBMC_CRT_VERT_TOTAL_DISP_END(x) … #define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK … #define HIBMC_CRT_VERT_SYNC … #define HIBMC_CRT_VERT_SYNC_HEIGHT(x) … #define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK … #define HIBMC_CRT_VERT_SYNC_START(x) … #define HIBMC_CRT_VERT_SYNC_START_MASK … /* Auto Centering */ #define HIBMC_CRT_AUTO_CENTERING_TL … #define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) … #define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK … #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) … #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK … #define HIBMC_CRT_AUTO_CENTERING_BR … #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) … #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK … #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) … #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK … /* register to control panel output */ #define HIBMC_DISPLAY_CONTROL_HISILE … #define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) … #define HIBMC_DISPLAY_CONTROL_PANELDATE(x) … #define HIBMC_DISPLAY_CONTROL_FPEN(x) … #define HIBMC_DISPLAY_CONTROL_VBIASEN(x) … #define HIBMC_RAW_INTERRUPT … #define HIBMC_RAW_INTERRUPT_VBLANK(x) … #define HIBMC_RAW_INTERRUPT_VBLANK_MASK … #define HIBMC_RAW_INTERRUPT_EN … #define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) … #define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK … /* register and values for PLL control */ #define CRT_PLL1_HS … #define CRT_PLL1_HS_OUTER_BYPASS(x) … #define CRT_PLL1_HS_INTER_BYPASS(x) … #define CRT_PLL1_HS_POWERON(x) … #define CRT_PLL1_HS_25MHZ … #define CRT_PLL1_HS_40MHZ … #define CRT_PLL1_HS_65MHZ … #define CRT_PLL1_HS_78MHZ … #define CRT_PLL1_HS_74MHZ … #define CRT_PLL1_HS_80MHZ … #define CRT_PLL1_HS_80MHZ_1152 … #define CRT_PLL1_HS_106MHZ … #define CRT_PLL1_HS_108MHZ … #define CRT_PLL1_HS_162MHZ … #define CRT_PLL1_HS_148MHZ … #define CRT_PLL1_HS_193MHZ … #define CRT_PLL2_HS … #define CRT_PLL2_HS_25MHZ … #define CRT_PLL2_HS_40MHZ … #define CRT_PLL2_HS_65MHZ … #define CRT_PLL2_HS_78MHZ … #define CRT_PLL2_HS_74MHZ … #define CRT_PLL2_HS_80MHZ … #define CRT_PLL2_HS_106MHZ … #define CRT_PLL2_HS_108MHZ … #define CRT_PLL2_HS_162MHZ … #define CRT_PLL2_HS_148MHZ … #define CRT_PLL2_HS_193MHZ … #define HIBMC_CRT_PALETTE … #define HIBMC_FIELD(field, value) … #endif
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