/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __DRM_MCDE_DSI_REGS #define __DRM_MCDE_DSI_REGS #define DSI_MCTL_INTEGRATION_MODE … #define DSI_MCTL_MAIN_DATA_CTL … #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN … #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE … #define DSI_MCTL_MAIN_DATA_CTL_VID_EN … #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL … #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL … #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN … #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN … #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN … #define DSI_MCTL_MAIN_DATA_CTL_READ_EN … #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN … #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC … #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM … #define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN … #define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN … #define DSI_MCTL_MAIN_DATA_CTL_DLX_REMAP_EN … #define DSI_MCTL_MAIN_DATA_CTL_TE_POLLING_EN … #define DSI_MCTL_MAIN_PHY_CTL … #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN … #define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE … #define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS … #define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN … #define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN … #define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN … #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT … #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK … #define DSI_MCTL_MAIN_PHY_CTL_CLOCK_FORCE_STOP_MODE … #define DSI_MCTL_PLL_CTL … #define DSI_MCTL_LANE_STS … #define DSI_MCTL_DPHY_TIMEOUT … #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT … #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK … #define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT … #define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK … #define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT … #define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK … #define DSI_MCTL_ULPOUT_TIME … #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT … #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK … #define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT … #define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK … #define DSI_MCTL_DPHY_STATIC … #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK … #define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK … #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1 … #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1 … #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2 … #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2 … #define DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT … #define DSI_MCTL_DPHY_STATIC_UI_X4_MASK … #define DSI_MCTL_MAIN_EN … #define DSI_MCTL_MAIN_EN_PLL_START … #define DSI_MCTL_MAIN_EN_CKLANE_EN … #define DSI_MCTL_MAIN_EN_DAT1_EN … #define DSI_MCTL_MAIN_EN_DAT2_EN … #define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ … #define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ … #define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ … #define DSI_MCTL_MAIN_EN_IF1_EN … #define DSI_MCTL_MAIN_EN_IF2_EN … #define DSI_MCTL_MAIN_STS … #define DSI_MCTL_MAIN_STS_PLL_LOCK … #define DSI_MCTL_MAIN_STS_CLKLANE_READY … #define DSI_MCTL_MAIN_STS_DAT1_READY … #define DSI_MCTL_MAIN_STS_DAT2_READY … #define DSI_MCTL_MAIN_STS_HSTX_TO_ERR … #define DSI_MCTL_MAIN_STS_LPRX_TO_ERR … #define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK … #define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK … #define DSI_MCTL_DPHY_ERR … #define DSI_INT_VID_RDDATA … #define DSI_INT_VID_GNT … #define DSI_INT_CMD_RDDATA … #define DSI_INT_CMD_GNT … #define DSI_INT_INTERRUPT_CTL … #define DSI_CMD_MODE_CTL … #define DSI_CMD_MODE_CTL_IF1_ID_SHIFT … #define DSI_CMD_MODE_CTL_IF1_ID_MASK … #define DSI_CMD_MODE_CTL_IF2_ID_SHIFT … #define DSI_CMD_MODE_CTL_IF2_ID_MASK … #define DSI_CMD_MODE_CTL_IF1_LP_EN … #define DSI_CMD_MODE_CTL_IF2_LP_EN … #define DSI_CMD_MODE_CTL_ARB_MODE … #define DSI_CMD_MODE_CTL_ARB_PRI … #define DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT … #define DSI_CMD_MODE_CTL_FIL_VALUE_MASK … #define DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT … #define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK … #define DSI_CMD_MODE_STS … #define DSI_CMD_MODE_STS_ERR_NO_TE … #define DSI_CMD_MODE_STS_ERR_TE_MISS … #define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN … #define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN … #define DSI_CMD_MODE_STS_ERR_UNWANTED_RD … #define DSI_CMD_MODE_STS_CSM_RUNNING … #define DSI_DIRECT_CMD_SEND … #define DSI_DIRECT_CMD_MAIN_SETTINGS … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN … #define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT … #define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK … #define DSI_DIRECT_CMD_STS … #define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION … #define DSI_DIRECT_CMD_STS_WRITE_COMPLETED … #define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED … #define DSI_DIRECT_CMD_STS_READ_COMPLETED … #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT … #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED … #define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED … #define DSI_DIRECT_CMD_STS_TE_RECEIVED … #define DSI_DIRECT_CMD_STS_BTA_COMPLETED … #define DSI_DIRECT_CMD_STS_BTA_FINISHED … #define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR … #define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK … #define DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT … #define DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT … #define DSI_DIRECT_CMD_STS_ACK_VAL_MASK … #define DSI_DIRECT_CMD_RD_INIT … #define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT … #define DSI_DIRECT_CMD_RD_INIT_RESET_MASK … #define DSI_DIRECT_CMD_WRDAT0 … #define DSI_DIRECT_CMD_WRDAT1 … #define DSI_DIRECT_CMD_WRDAT2 … #define DSI_DIRECT_CMD_WRDAT3 … #define DSI_DIRECT_CMD_RDDAT … #define DSI_DIRECT_CMD_RD_PROPERTY … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT … #define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK … #define DSI_DIRECT_CMD_RD_STS … #define DSI_VID_MAIN_CTL … #define DSI_VID_MAIN_CTL_START_MODE_SHIFT … #define DSI_VID_MAIN_CTL_START_MODE_MASK … #define DSI_VID_MAIN_CTL_STOP_MODE_SHIFT … #define DSI_VID_MAIN_CTL_STOP_MODE_MASK … #define DSI_VID_MAIN_CTL_VID_ID_SHIFT … #define DSI_VID_MAIN_CTL_VID_ID_MASK … #define DSI_VID_MAIN_CTL_HEADER_SHIFT … #define DSI_VID_MAIN_CTL_HEADER_MASK … #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS … #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS … #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE … #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS … #define DSI_VID_MAIN_CTL_BURST_MODE … #define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE … #define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL … #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL … #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING … #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 … #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 … #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL … #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING … #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 … #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 … #define DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT … #define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK … #define DSI_VID_VSIZE … #define DSI_VID_VSIZE_VSA_LENGTH_SHIFT … #define DSI_VID_VSIZE_VSA_LENGTH_MASK … #define DSI_VID_VSIZE_VBP_LENGTH_SHIFT … #define DSI_VID_VSIZE_VBP_LENGTH_MASK … #define DSI_VID_VSIZE_VFP_LENGTH_SHIFT … #define DSI_VID_VSIZE_VFP_LENGTH_MASK … #define DSI_VID_VSIZE_VACT_LENGTH_SHIFT … #define DSI_VID_VSIZE_VACT_LENGTH_MASK … #define DSI_VID_HSIZE1 … #define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT … #define DSI_VID_HSIZE1_HSA_LENGTH_MASK … #define DSI_VID_HSIZE1_HBP_LENGTH_SHIFT … #define DSI_VID_HSIZE1_HBP_LENGTH_MASK … #define DSI_VID_HSIZE1_HFP_LENGTH_SHIFT … #define DSI_VID_HSIZE1_HFP_LENGTH_MASK … #define DSI_VID_HSIZE2 … #define DSI_VID_HSIZE2_RGB_SIZE_SHIFT … #define DSI_VID_HSIZE2_RGB_SIZE_MASK … #define DSI_VID_BLKSIZE1 … #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT … #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK … #define DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT … #define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK … #define DSI_VID_BLKSIZE2 … #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT … #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK … #define DSI_VID_PCK_TIME … #define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT … #define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK … #define DSI_VID_DPHY_TIME … #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT … #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK … #define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT … #define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK … #define DSI_VID_MODE_STS … #define DSI_VID_MODE_STS_VSG_RUNNING … #define DSI_VID_MODE_STS_ERR_MISSING_DATA … #define DSI_VID_MODE_STS_ERR_MISSING_HSYNC … #define DSI_VID_MODE_STS_ERR_MISSING_VSYNC … #define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH … #define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT … #define DSI_VID_MODE_STS_ERR_BURSTWRITE … #define DSI_VID_MODE_STS_ERR_LINEWRITE … #define DSI_VID_MODE_STS_ERR_LONGREAD … #define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH … #define DSI_VID_MODE_STS_VSG_RECOVERY … #define DSI_VID_VCA_SETTING1 … #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT … #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK … #define DSI_VID_VCA_SETTING1_BURST_LP … #define DSI_VID_VCA_SETTING2 … #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT … #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK … #define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT … #define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK … #define DSI_CMD_MODE_STS_CTL … #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN … #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN … #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN … #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN … #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN … #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN … #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE … #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE … #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE … #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE … #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE … #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE … #define DSI_DIRECT_CMD_STS_CTL … #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN … #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN … #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN … #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN … #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN … #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN … #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN … #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN … #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN … #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN … #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN … #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE … #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE … #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE … #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE … #define DSI_VID_MODE_STS_CTL … #define DSI_VID_MODE_STS_CTL_VSG_RUNNING … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC … #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH … #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT … #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE … #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE … #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD … #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH … #define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE … #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE … #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE … #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE … #define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE … #define DSI_TG_STS_CTL … #define DSI_MCTL_DHPY_ERR_CTL … #define DSI_MCTL_MAIN_STS_CLR … #define DSI_CMD_MODE_STS_CLR … #define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR … #define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR … #define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR … #define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR … #define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR … #define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR … #define DSI_DIRECT_CMD_STS_CLR … #define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR … #define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR … #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR … #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR … #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR … #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR … #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR … #define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR … #define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR … #define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR … #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR … #define DSI_DIRECT_CMD_RD_STS_CLR … #define DSI_VID_MODE_STS_CLR … #define DSI_TG_STS_CLR … #define DSI_MCTL_DPHY_ERR_CLR … #define DSI_MCTL_MAIN_STS_FLAG … #define DSI_CMD_MODE_STS_FLAG … #define DSI_DIRECT_CMD_STS_FLAG … #define DSI_DIRECT_CMD_RD_STS_FLAG … #define DSI_VID_MODE_STS_FLAG … #define DSI_TG_STS_FLAG … #define DSI_DPHY_LANES_TRIM … #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT … #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK … #define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1 … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1 … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1 … #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1 … #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT … #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK … #define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT … #define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK … #define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT … #define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK … #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 … #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK … #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK … #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2 … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2 … #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2 … #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2 … #define DSI_ID_REG … #endif /* __DRM_MCDE_DSI_REGS */
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