/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Author: Tomi Valkeinen <[email protected]> */ #ifndef __TIDSS_IRQ_H__ #define __TIDSS_IRQ_H__ #include <linux/types.h> #include "tidss_drv.h" /* * The IRQ status from various DISPC IRQ registers are packed into a single * value, where the bits are defined as follows: * * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> | * bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | | * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 | * * device bits: D = OCP error * WB bits: f = frame done wb, o = wb buffer overflow, * u = wb buffer uncomplete * vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost * plane bits: U = fifo underflow */ #define DSS_IRQ_DEVICE_OCP_ERR … #define DSS_IRQ_DEVICE_FRAMEDONEWB … #define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW … #define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR … #define DSS_IRQ_DEVICE_WB_MASK … #define DSS_IRQ_VP_BIT_N(ch, bit) … #define DSS_IRQ_PLANE_BIT_N(plane, bit) … #define DSS_IRQ_VP_BIT(ch, bit) … #define DSS_IRQ_PLANE_BIT(plane, bit) … static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch) { … } static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane) { … } #define DSS_IRQ_VP_FRAME_DONE(ch) … #define DSS_IRQ_VP_VSYNC_EVEN(ch) … #define DSS_IRQ_VP_VSYNC_ODD(ch) … #define DSS_IRQ_VP_SYNC_LOST(ch) … #define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) … struct drm_crtc; struct drm_device; struct tidss_device; void tidss_irq_enable_vblank(struct drm_crtc *crtc); void tidss_irq_disable_vblank(struct drm_crtc *crtc); int tidss_irq_install(struct drm_device *ddev, unsigned int irq); void tidss_irq_uninstall(struct drm_device *ddev); void tidss_irq_resume(struct tidss_device *tidss); #endif
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