/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ * Author: Jyri Sarha <[email protected]> */ #ifndef __TIDSS_DISPC_REGS_H #define __TIDSS_DISPC_REGS_H enum dispc_common_regs { … }; /* * dispc_common_regmap should be defined as const u16 * and pointing * to a valid dss common register map for the platform, before the * macros bellow can be used. */ #define REG(r) … #define DSS_REVISION … #define DSS_SYSCONFIG … #define DSS_SYSSTATUS … #define DISPC_IRQ_EOI … #define DISPC_IRQSTATUS_RAW … #define DISPC_IRQSTATUS … #define DISPC_IRQENABLE_SET … #define DISPC_IRQENABLE_CLR … #define DISPC_VID_IRQENABLE(n) … #define DISPC_VID_IRQSTATUS(n) … #define DISPC_VP_IRQENABLE(n) … #define DISPC_VP_IRQSTATUS(n) … #define WB_IRQENABLE … #define WB_IRQSTATUS … #define DISPC_GLOBAL_MFLAG_ATTRIBUTE … #define DISPC_GLOBAL_OUTPUT_ENABLE … #define DISPC_GLOBAL_BUFFER … #define DSS_CBA_CFG … #define DISPC_DBG_CONTROL … #define DISPC_DBG_STATUS … #define DISPC_CLKGATING_DISABLE … #define DISPC_SECURE_DISABLE … #define FBDC_REVISION_1 … #define FBDC_REVISION_2 … #define FBDC_REVISION_3 … #define FBDC_REVISION_4 … #define FBDC_REVISION_5 … #define FBDC_REVISION_6 … #define FBDC_COMMON_CONTROL … #define FBDC_CONSTANT_COLOR_0 … #define FBDC_CONSTANT_COLOR_1 … #define DISPC_CONNECTIONS … #define DISPC_MSS_VP1 … #define DISPC_MSS_VP3 … /* VID */ #define DISPC_VID_ACCUH_0 … #define DISPC_VID_ACCUH_1 … #define DISPC_VID_ACCUH2_0 … #define DISPC_VID_ACCUH2_1 … #define DISPC_VID_ACCUV_0 … #define DISPC_VID_ACCUV_1 … #define DISPC_VID_ACCUV2_0 … #define DISPC_VID_ACCUV2_1 … #define DISPC_VID_ATTRIBUTES … #define DISPC_VID_ATTRIBUTES2 … #define DISPC_VID_BA_0 … #define DISPC_VID_BA_1 … #define DISPC_VID_BA_UV_0 … #define DISPC_VID_BA_UV_1 … #define DISPC_VID_BUF_SIZE_STATUS … #define DISPC_VID_BUF_THRESHOLD … #define DISPC_VID_CSC_COEF(n) … #define DISPC_VID_FIRH … #define DISPC_VID_FIRH2 … #define DISPC_VID_FIRV … #define DISPC_VID_FIRV2 … #define DISPC_VID_FIR_COEFS_H0 … #define DISPC_VID_FIR_COEF_H0(phase) … #define DISPC_VID_FIR_COEFS_H0_C … #define DISPC_VID_FIR_COEF_H0_C(phase) … #define DISPC_VID_FIR_COEFS_H12 … #define DISPC_VID_FIR_COEF_H12(phase) … #define DISPC_VID_FIR_COEFS_H12_C … #define DISPC_VID_FIR_COEF_H12_C(phase) … #define DISPC_VID_FIR_COEFS_V0 … #define DISPC_VID_FIR_COEF_V0(phase) … #define DISPC_VID_FIR_COEFS_V0_C … #define DISPC_VID_FIR_COEF_V0_C(phase) … #define DISPC_VID_FIR_COEFS_V12 … #define DISPC_VID_FIR_COEF_V12(phase) … #define DISPC_VID_FIR_COEFS_V12_C … #define DISPC_VID_FIR_COEF_V12_C(phase) … #define DISPC_VID_GLOBAL_ALPHA … #define DISPC_VID_K2G_IRQENABLE … #define DISPC_VID_K2G_IRQSTATUS … #define DISPC_VID_MFLAG_THRESHOLD … #define DISPC_VID_PICTURE_SIZE … #define DISPC_VID_PIXEL_INC … #define DISPC_VID_K2G_POSITION … #define DISPC_VID_PRELOAD … #define DISPC_VID_ROW_INC … #define DISPC_VID_SIZE … #define DISPC_VID_BA_EXT_0 … #define DISPC_VID_BA_EXT_1 … #define DISPC_VID_BA_UV_EXT_0 … #define DISPC_VID_BA_UV_EXT_1 … #define DISPC_VID_CSC_COEF7 … #define DISPC_VID_ROW_INC_UV … #define DISPC_VID_CLUT … #define DISPC_VID_SAFETY_ATTRIBUTES … #define DISPC_VID_SAFETY_CAPT_SIGNATURE … #define DISPC_VID_SAFETY_POSITION … #define DISPC_VID_SAFETY_REF_SIGNATURE … #define DISPC_VID_SAFETY_SIZE … #define DISPC_VID_SAFETY_LFSR_SEED … #define DISPC_VID_LUMAKEY … #define DISPC_VID_DMA_BUFSIZE … /* OVR */ #define DISPC_OVR_CONFIG … #define DISPC_OVR_VIRTVP … #define DISPC_OVR_DEFAULT_COLOR … #define DISPC_OVR_DEFAULT_COLOR2 … #define DISPC_OVR_TRANS_COLOR_MAX … #define DISPC_OVR_TRANS_COLOR_MAX2 … #define DISPC_OVR_TRANS_COLOR_MIN … #define DISPC_OVR_TRANS_COLOR_MIN2 … #define DISPC_OVR_ATTRIBUTES(n) … #define DISPC_OVR_ATTRIBUTES2(n) … /* VP */ #define DISPC_VP_CONFIG … #define DISPC_VP_CONTROL … #define DISPC_VP_CSC_COEF0 … #define DISPC_VP_CSC_COEF1 … #define DISPC_VP_CSC_COEF2 … #define DISPC_VP_DATA_CYCLE_0 … #define DISPC_VP_DATA_CYCLE_1 … #define DISPC_VP_K2G_GAMMA_TABLE … #define DISPC_VP_K2G_IRQENABLE … #define DISPC_VP_K2G_IRQSTATUS … #define DISPC_VP_DATA_CYCLE_2 … #define DISPC_VP_LINE_NUMBER … #define DISPC_VP_POL_FREQ … #define DISPC_VP_SIZE_SCREEN … #define DISPC_VP_TIMING_H … #define DISPC_VP_TIMING_V … #define DISPC_VP_CSC_COEF3 … #define DISPC_VP_CSC_COEF4 … #define DISPC_VP_CSC_COEF5 … #define DISPC_VP_CSC_COEF6 … #define DISPC_VP_CSC_COEF7 … #define DISPC_VP_SAFETY_ATTRIBUTES_0 … #define DISPC_VP_SAFETY_ATTRIBUTES_1 … #define DISPC_VP_SAFETY_ATTRIBUTES_2 … #define DISPC_VP_SAFETY_ATTRIBUTES_3 … #define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 … #define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 … #define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 … #define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 … #define DISPC_VP_SAFETY_POSITION_0 … #define DISPC_VP_SAFETY_POSITION_1 … #define DISPC_VP_SAFETY_POSITION_2 … #define DISPC_VP_SAFETY_POSITION_3 … #define DISPC_VP_SAFETY_REF_SIGNATURE_0 … #define DISPC_VP_SAFETY_REF_SIGNATURE_1 … #define DISPC_VP_SAFETY_REF_SIGNATURE_2 … #define DISPC_VP_SAFETY_REF_SIGNATURE_3 … #define DISPC_VP_SAFETY_SIZE_0 … #define DISPC_VP_SAFETY_SIZE_1 … #define DISPC_VP_SAFETY_SIZE_2 … #define DISPC_VP_SAFETY_SIZE_3 … #define DISPC_VP_SAFETY_LFSR_SEED … #define DISPC_VP_GAMMA_TABLE … #define DISPC_VP_DSS_OLDI_CFG … #define DISPC_VP_DSS_OLDI_STATUS … #define DISPC_VP_DSS_OLDI_LB … #define DISPC_VP_DSS_MERGE_SPLIT … #define DISPC_VP_DSS_DMA_THREADSIZE … #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS … /* * OLDI IO_CTRL register offsets. On AM654 the registers are found * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL * register range. */ #define OLDI_DAT0_IO_CTRL … #define OLDI_DAT1_IO_CTRL … #define OLDI_DAT2_IO_CTRL … #define OLDI_DAT3_IO_CTRL … #define OLDI_CLK_IO_CTRL … #define OLDI_PWRDN_TX … #endif /* __TIDSS_DISPC_REGS_H */
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