#ifndef __LINUX_MFD_BD9571MWV_H
#define __LINUX_MFD_BD9571MWV_H
#include <linux/device.h>
#include <linux/regmap.h>
#define BD9571MWV_VENDOR_CODE …
#define BD9571MWV_VENDOR_CODE_VAL …
#define BD9571MWV_PRODUCT_CODE …
#define BD9571MWV_PRODUCT_CODE_BD9571MWV …
#define BD9571MWV_PRODUCT_CODE_BD9574MWF …
#define BD9571MWV_PRODUCT_REVISION …
#define BD9571MWV_I2C_FUSA_MODE …
#define BD9571MWV_I2C_MD2_E1_BIT_1 …
#define BD9571MWV_I2C_MD2_E1_BIT_2 …
#define BD9571MWV_BKUP_MODE_CNT …
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK …
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0 …
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1 …
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C …
#define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C …
#define BD9571MWV_BKUP_MODE_STATUS …
#define BD9571MWV_BKUP_RECOVERY_CNT …
#define BD9571MWV_BKUP_CTRL_TIM_CNT …
#define BD9571MWV_WAITBKUP_WDT_CNT …
#define BD9571MWV_128H_TIM_CNT …
#define BD9571MWV_QLLM_CNT …
#define BD9571MWV_AVS_SET_MONI …
#define BD9571MWV_AVS_SET_MONI_MASK …
#define BD9571MWV_AVS_VD09_VID(n) …
#define BD9571MWV_AVS_DVFS_VID(n) …
#define BD9571MWV_VD18_VID …
#define BD9571MWV_VD25_VID …
#define BD9571MWV_VD33_VID …
#define BD9571MWV_DVFS_VINIT …
#define BD9574MWF_VD09_VINIT …
#define BD9571MWV_DVFS_SETVMAX …
#define BD9571MWV_DVFS_BOOSTVID …
#define BD9571MWV_DVFS_SETVID …
#define BD9571MWV_DVFS_MONIVDAC …
#define BD9571MWV_DVFS_PGD_CNT …
#define BD9571MWV_GPIO_DIR …
#define BD9571MWV_GPIO_OUT …
#define BD9571MWV_GPIO_IN …
#define BD9571MWV_GPIO_DEB …
#define BD9571MWV_GPIO_INT_SET …
#define BD9571MWV_GPIO_INT …
#define BD9571MWV_GPIO_INTMASK …
#define BD9574MWF_GPIO_MUX …
#define BD9571MWV_REG_KEEP(n) …
#define BD9571MWV_PMIC_INTERNAL_STATUS …
#define BD9571MWV_PROT_ERROR_STATUS0 …
#define BD9571MWV_PROT_ERROR_STATUS1 …
#define BD9571MWV_PROT_ERROR_STATUS2 …
#define BD9571MWV_PROT_ERROR_STATUS3 …
#define BD9571MWV_PROT_ERROR_STATUS4 …
#define BD9574MWF_PROT_ERROR_STATUS5 …
#define BD9574MWF_SYSTEM_ERROR_STATUS …
#define BD9571MWV_INT_INTREQ …
#define BD9571MWV_INT_INTREQ_MD1_INT …
#define BD9571MWV_INT_INTREQ_MD2_E1_INT …
#define BD9571MWV_INT_INTREQ_MD2_E2_INT …
#define BD9571MWV_INT_INTREQ_PROT_ERR_INT …
#define BD9571MWV_INT_INTREQ_GP_INT …
#define BD9571MWV_INT_INTREQ_128H_OF_INT …
#define BD9571MWV_INT_INTREQ_WDT_OF_INT …
#define BD9571MWV_INT_INTREQ_BKUP_TRG_INT …
#define BD9571MWV_INT_INTMASK …
#define BD9574MWF_SSCG_CNT …
#define BD9574MWF_POFFB_MRB …
#define BD9574MWF_SMRB_WR_PROT …
#define BD9574MWF_SMRB_ASSERT …
#define BD9574MWF_SMRB_STATUS …
#define BD9571MWV_ACCESS_KEY …
enum bd9571mwv_irqs { … };
#endif