// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ * Author: Jyri Sarha <[email protected]> */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/sys_soc.h> #include <drm/drm_blend.h> #include <drm/drm_fourcc.h> #include <drm/drm_fb_dma_helper.h> #include <drm/drm_framebuffer.h> #include <drm/drm_gem_dma_helper.h> #include <drm/drm_panel.h> #include "tidss_crtc.h" #include "tidss_dispc.h" #include "tidss_drv.h" #include "tidss_irq.h" #include "tidss_plane.h" #include "tidss_dispc_regs.h" #include "tidss_scale_coefs.h" static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = …; const struct dispc_features dispc_k2g_feats = …; static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = …; const struct dispc_features dispc_am65x_feats = …; static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = …; const struct dispc_features dispc_j721e_feats = …; const struct dispc_features dispc_am625_feats = …; const struct dispc_features dispc_am62a7_feats = …; static const u16 *dispc_common_regmap; struct dss_vp_data { … }; struct dispc_device { … }; static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) { … } static u32 dispc_read(struct dispc_device *dispc, u16 reg) { … } static void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) { … } static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) { … } static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, u16 reg, u32 val) { … } static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) { … } static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, u16 reg, u32 val) { … } static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) { … } /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ static u32 FLD_MASK(u32 start, u32 end) { … } static u32 FLD_VAL(u32 val, u32 start, u32 end) { … } static u32 FLD_GET(u32 val, u32 start, u32 end) { … } static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) { … } static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) { … } static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, u32 start, u32 end) { … } static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, u32 start, u32 end) { … } static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, u32 val, u32 start, u32 end) { … } static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 start, u32 end) { … } static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, u32 start, u32 end) { … } __maybe_unused static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, u32 start, u32 end) { … } static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { … } static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { … } static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport) { … } static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) { … } static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) { … } static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, u32 hw_videoport, dispc_irq_t vpstat) { … } static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) { … } static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { … } static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, u32 hw_videoport, dispc_irq_t vpstat) { … } static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) { … } static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { … } static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t mask) { … } static dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) { … } static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) { … } static void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) { … } static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, u32 hw_videoport, dispc_irq_t vpstat) { … } static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) { … } static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { … } static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, u32 hw_videoport, dispc_irq_t vpstat) { … } static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) { … } static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { … } static void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) { … } static dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) { … } static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) { … } static void dispc_k3_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) { … } dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) { … } void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) { … } enum dispc_oldi_mode_reg_val { … }; struct dispc_bus_format { … }; static const struct dispc_bus_format dispc_bus_formats[] = …; static const struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, u32 hw_videoport, u32 bus_fmt, u32 bus_flags) { … } int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state) { … } static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) { … } static void dispc_set_num_datalines(struct dispc_device *dispc, u32 hw_videoport, int num_lines) { … } static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, const struct dispc_bus_format *fmt) { … } void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state) { … } void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state) { … } void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { … } void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { … } bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { … } void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { … } enum c8_to_c12_mode { … }; static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) { … } static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) { … } static void dispc_vp_set_default_color(struct dispc_device *dispc, u32 hw_videoport, u32 default_color) { … } enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, u32 hw_videoport, const struct drm_display_mode *mode) { … } int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) { … } void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) { … } /* * Calculate the percentage difference between the requested pixel clock rate * and the effective rate resulting from calculating the clock divider value. */ static unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) { … } int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, unsigned long rate) { … } /* OVR */ static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { … } static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { … } static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { … } void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { … } void dispc_ovr_enable_layer(struct dispc_device *dispc, u32 hw_videoport, u32 layer, bool enable) { … } /* CSC */ enum csc_ctm { … }; enum csc_yuv2rgb { … }; enum csc_rgb2yuv { … }; struct dispc_csc_coef { … }; #define DISPC_CSC_REGVAL_LEN … static void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) { … } #define CVAL … static void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) { … } __maybe_unused static void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval) { … } static void dispc_csc_cpr_regval(const struct dispc_csc_coef *csc, u32 *regval) { … } #undef CVAL static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) { … } static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, const struct dispc_csc_coef *csc) { … } /* YUV -> RGB, ITU-R BT.601, full range */ static const struct dispc_csc_coef csc_yuv2rgb_bt601_full = …; /* YUV -> RGB, ITU-R BT.601, limited range */ static const struct dispc_csc_coef csc_yuv2rgb_bt601_lim = …; /* YUV -> RGB, ITU-R BT.709, full range */ static const struct dispc_csc_coef csc_yuv2rgb_bt709_full = …; /* YUV -> RGB, ITU-R BT.709, limited range */ static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = …; static const struct { … } dispc_csc_table[] = …; static const struct dispc_csc_coef *dispc_find_csc(enum drm_color_encoding encoding, enum drm_color_range range) { … } static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state) { … } static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { … } /* SCALER */ static u32 dispc_calc_fir_inc(u32 in, u32 out) { … } enum dispc_vid_fir_coef_set { … }; static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, u32 hw_plane, enum dispc_vid_fir_coef_set coef_set, const struct tidss_scale_coefs *coefs) { … } static bool dispc_fourcc_is_yuv(u32 fourcc) { … } struct dispc_scaling_params { … }; static int dispc_vid_calc_scaling(struct dispc_device *dispc, const struct drm_plane_state *state, struct dispc_scaling_params *sp, bool lite_plane) { … } static void dispc_vid_set_scaling(struct dispc_device *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) { … } /* OTHER */ static const struct { … } dispc_color_formats[] = …; static void dispc_plane_set_pixel_format(struct dispc_device *dispc, u32 hw_plane, u32 fourcc) { … } const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) { … } static s32 pixinc(int pixels, u8 ps) { … } int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) { … } static dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state) { … } static dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state) { … } void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) { … } void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { … } static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) { … } static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { … } static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { … } static void dispc_k2g_plane_init(struct dispc_device *dispc) { … } static void dispc_k3_plane_init(struct dispc_device *dispc) { … } static void dispc_plane_init(struct dispc_device *dispc) { … } static void dispc_vp_init(struct dispc_device *dispc) { … } static void dispc_initial_config(struct dispc_device *dispc) { … } static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, u32 hw_videoport) { … } static void dispc_vp_write_gamma_table(struct dispc_device *dispc, u32 hw_videoport) { … } static const struct drm_color_lut dispc_vp_gamma_default_lut[] = …; static void dispc_vp_set_gamma(struct dispc_device *dispc, u32 hw_videoport, const struct drm_color_lut *lut, unsigned int length) { … } static s16 dispc_S31_32_to_s2_8(s64 coef) { … } static void dispc_k2g_cpr_from_ctm(const struct drm_color_ctm *ctm, struct dispc_csc_coef *cpr) { … } #define CVAL … static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, u32 *regval) { … } #undef CVAL static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, const struct dispc_csc_coef *csc) { … } static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, struct drm_color_ctm *ctm) { … } static s16 dispc_S31_32_to_s3_8(s64 coef) { … } static void dispc_csc_from_ctm(const struct drm_color_ctm *ctm, struct dispc_csc_coef *cpr) { … } static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, const struct dispc_csc_coef *csc) { … } static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, struct drm_color_ctm *ctm) { … } static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, bool newmodeset) { … } void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, bool newmodeset) { … } int dispc_runtime_suspend(struct dispc_device *dispc) { … } int dispc_runtime_resume(struct dispc_device *dispc) { … } void dispc_remove(struct tidss_device *tidss) { … } static int dispc_iomap_resource(struct platform_device *pdev, const char *name, void __iomem **base) { … } static int dispc_init_am65x_oldi_io_ctrl(struct device *dev, struct dispc_device *dispc) { … } static void dispc_init_errata(struct dispc_device *dispc) { … } /* * K2G display controller does not support soft reset, so we do a basic manual * reset here: make sure the IRQs are masked and VPs are disabled. */ static void dispc_softreset_k2g(struct dispc_device *dispc) { … } static int dispc_softreset(struct dispc_device *dispc) { … } static int dispc_init_hw(struct dispc_device *dispc) { … } int dispc_init(struct tidss_device *tidss) { … }
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