// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020 Unisoc Inc. */ #include <linux/component.h> #include <linux/delay.h> #include <linux/dma-buf.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/wait.h> #include <linux/workqueue.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> #include <drm/drm_fb_dma_helper.h> #include <drm/drm_framebuffer.h> #include <drm/drm_gem_dma_helper.h> #include <drm/drm_gem_framebuffer_helper.h> #include "sprd_drm.h" #include "sprd_dpu.h" #include "sprd_dsi.h" /* Global control registers */ #define REG_DPU_CTRL … #define REG_DPU_CFG0 … #define REG_PANEL_SIZE … #define REG_BLEND_SIZE … #define REG_BG_COLOR … /* Layer0 control registers */ #define REG_LAY_BASE_ADDR0 … #define REG_LAY_BASE_ADDR1 … #define REG_LAY_BASE_ADDR2 … #define REG_LAY_CTRL … #define REG_LAY_SIZE … #define REG_LAY_PITCH … #define REG_LAY_POS … #define REG_LAY_ALPHA … #define REG_LAY_CROP_START … /* Interrupt control registers */ #define REG_DPU_INT_EN … #define REG_DPU_INT_CLR … #define REG_DPU_INT_STS … /* DPI control registers */ #define REG_DPI_CTRL … #define REG_DPI_H_TIMING … #define REG_DPI_V_TIMING … /* MMU control registers */ #define REG_MMU_EN … #define REG_MMU_VPN_RANGE … #define REG_MMU_PPN1 … #define REG_MMU_RANGE1 … #define REG_MMU_PPN2 … #define REG_MMU_RANGE2 … /* Global control bits */ #define BIT_DPU_RUN … #define BIT_DPU_STOP … #define BIT_DPU_REG_UPDATE … #define BIT_DPU_IF_EDPI … /* Layer control bits */ #define BIT_DPU_LAY_EN … #define BIT_DPU_LAY_LAYER_ALPHA … #define BIT_DPU_LAY_COMBO_ALPHA … #define BIT_DPU_LAY_FORMAT_YUV422_2PLANE … #define BIT_DPU_LAY_FORMAT_YUV420_2PLANE … #define BIT_DPU_LAY_FORMAT_YUV420_3PLANE … #define BIT_DPU_LAY_FORMAT_ARGB8888 … #define BIT_DPU_LAY_FORMAT_RGB565 … #define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3 … #define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0 … #define BIT_DPU_LAY_NO_SWITCH … #define BIT_DPU_LAY_RB_OR_UV_SWITCH … #define BIT_DPU_LAY_MODE_BLEND_NORMAL … #define BIT_DPU_LAY_MODE_BLEND_PREMULT … #define BIT_DPU_LAY_ROTATION_0 … #define BIT_DPU_LAY_ROTATION_90 … #define BIT_DPU_LAY_ROTATION_180 … #define BIT_DPU_LAY_ROTATION_270 … #define BIT_DPU_LAY_ROTATION_0_M … #define BIT_DPU_LAY_ROTATION_90_M … #define BIT_DPU_LAY_ROTATION_180_M … #define BIT_DPU_LAY_ROTATION_270_M … /* Interrupt control & status bits */ #define BIT_DPU_INT_DONE … #define BIT_DPU_INT_TE … #define BIT_DPU_INT_ERR … #define BIT_DPU_INT_UPDATE_DONE … #define BIT_DPU_INT_VSYNC … /* DPI control bits */ #define BIT_DPU_EDPI_TE_EN … #define BIT_DPU_EDPI_FROM_EXTERNAL_PAD … #define BIT_DPU_DPI_HALT_EN … static const u32 layer_fmts[] = …; struct sprd_plane { … }; static int dpu_wait_stop_done(struct sprd_dpu *dpu) { … } static int dpu_wait_update_done(struct sprd_dpu *dpu) { … } static u32 drm_format_to_dpu(struct drm_framebuffer *fb) { … } static u32 drm_rotation_to_dpu(struct drm_plane_state *state) { … } static u32 drm_blend_to_dpu(struct drm_plane_state *state) { … } static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state) { … } static void sprd_dpu_flip(struct sprd_dpu *dpu) { … } static void sprd_dpu_init(struct sprd_dpu *dpu) { … } static void sprd_dpu_fini(struct sprd_dpu *dpu) { … } static void sprd_dpi_init(struct sprd_dpu *dpu) { … } void sprd_dpu_run(struct sprd_dpu *dpu) { … } void sprd_dpu_stop(struct sprd_dpu *dpu) { … } static int sprd_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void sprd_plane_atomic_update(struct drm_plane *drm_plane, struct drm_atomic_state *state) { … } static void sprd_plane_atomic_disable(struct drm_plane *drm_plane, struct drm_atomic_state *state) { … } static void sprd_plane_create_properties(struct sprd_plane *plane, int index) { … } static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = …; static const struct drm_plane_funcs sprd_plane_funcs = …; static struct sprd_plane *sprd_planes_init(struct drm_device *drm) { … } static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc) { … } static void sprd_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void sprd_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void sprd_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static int sprd_crtc_enable_vblank(struct drm_crtc *crtc) { … } static void sprd_crtc_disable_vblank(struct drm_crtc *crtc) { … } static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = …; static const struct drm_crtc_funcs sprd_crtc_funcs = …; static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm, struct drm_plane *primary, struct device *dev) { … } static irqreturn_t sprd_dpu_isr(int irq, void *data) { … } static int sprd_dpu_context_init(struct sprd_dpu *dpu, struct device *dev) { … } static int sprd_dpu_bind(struct device *dev, struct device *master, void *data) { … } static const struct component_ops dpu_component_ops = …; static const struct of_device_id dpu_match_table[] = …; MODULE_DEVICE_TABLE(of, dpu_match_table); static int sprd_dpu_probe(struct platform_device *pdev) { … } static void sprd_dpu_remove(struct platform_device *pdev) { … } struct platform_driver sprd_dpu_driver = …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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