/* * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation; either version 2.1 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __GRU_INSTRUCTIONS_H__ #define __GRU_INSTRUCTIONS_H__ extern int gru_check_status_proc(void *cb); extern int gru_wait_proc(void *cb); extern void gru_wait_abort_proc(void *cb); /* * Architecture dependent functions */ #if defined(CONFIG_X86_64) #include <asm/cacheflush.h> #define __flush_cache(p) … #define gru_ordered_store_ulong(p, v) … #else #error "Unsupported architecture" #endif /* * Control block status and exception codes */ #define CBS_IDLE … #define CBS_EXCEPTION … #define CBS_ACTIVE … #define CBS_CALL_OS … /* CB substatus bitmasks */ #define CBSS_MSG_QUEUE_MASK … #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK … /* CB substatus message queue values (low 3 bits of substatus) */ #define CBSS_NO_ERROR … #define CBSS_LB_OVERFLOWED … #define CBSS_QLIMIT_REACHED … #define CBSS_PAGE_OVERFLOW … #define CBSS_AMO_NACKED … #define CBSS_PUT_NACKED … /* * Structure used to fetch exception detail for CBs that terminate with * CBS_EXCEPTION */ struct control_block_extended_exc_detail { … }; /* * Instruction formats */ /* * Generic instruction format. * This definition has precise bit field definitions. */ struct gru_instruction_bits { … }; /* * Generic instruction with friendlier names. This format is used * for inline instructions. */ struct gru_instruction { … }; /* Some shifts and masks for the low 64 bits of a GRU command */ #define GRU_CB_ICMD_SHFT … #define GRU_CB_ICMD_MASK … #define GRU_CB_XTYPE_SHFT … #define GRU_CB_XTYPE_MASK … #define GRU_CB_IAA0_SHFT … #define GRU_CB_IAA0_MASK … #define GRU_CB_IAA1_SHFT … #define GRU_CB_IAA1_MASK … #define GRU_CB_IMA_SHFT … #define GRU_CB_IMA_MASK … #define GRU_CB_OPC_SHFT … #define GRU_CB_OPC_MASK … #define GRU_CB_EXOPC_SHFT … #define GRU_CB_EXOPC_MASK … #define GRU_IDEF2_SHFT … #define GRU_IDEF2_MASK … #define GRU_ISTATUS_SHFT … #define GRU_ISTATUS_MASK … /* GRU instruction opcodes (opc field) */ #define OP_NOP … #define OP_BCOPY … #define OP_VLOAD … #define OP_IVLOAD … #define OP_VSTORE … #define OP_IVSTORE … #define OP_VSET … #define OP_IVSET … #define OP_MESQ … #define OP_GAMXR … #define OP_GAMIR … #define OP_GAMIRR … #define OP_GAMER … #define OP_GAMERR … #define OP_BSTORE … #define OP_VFLUSH … /* Extended opcodes values (exopc field) */ /* GAMIR - AMOs with implicit operands */ #define EOP_IR_FETCH … #define EOP_IR_CLR … #define EOP_IR_INC … #define EOP_IR_DEC … #define EOP_IR_QCHK1 … #define EOP_IR_QCHK2 … /* GAMIRR - Registered AMOs with implicit operands */ #define EOP_IRR_FETCH … #define EOP_IRR_CLR … #define EOP_IRR_INC … #define EOP_IRR_DEC … #define EOP_IRR_DECZ … /* GAMER - AMOs with explicit operands */ #define EOP_ER_SWAP … #define EOP_ER_OR … #define EOP_ER_AND … #define EOP_ER_XOR … #define EOP_ER_ADD … #define EOP_ER_CSWAP … #define EOP_ER_CADD … /* GAMERR - Registered AMOs with explicit operands */ #define EOP_ERR_SWAP … #define EOP_ERR_OR … #define EOP_ERR_AND … #define EOP_ERR_XOR … #define EOP_ERR_ADD … #define EOP_ERR_CSWAP … #define EOP_ERR_EPOLL … #define EOP_ERR_NPOLL … /* GAMXR - SGI Arithmetic unit */ #define EOP_XR_CSWAP … /* Transfer types (xtype field) */ #define XTYPE_B … #define XTYPE_S … #define XTYPE_W … #define XTYPE_DW … #define XTYPE_CL … /* Instruction access attributes (iaa0, iaa1 fields) */ #define IAA_RAM … #define IAA_NCRAM … #define IAA_MMIO … #define IAA_REGISTER … /* Instruction mode attributes (ima field) */ #define IMA_MAPPED … #define IMA_CB_DELAY … #define IMA_UNMAPPED … #define IMA_INTERRUPT … /* CBE ecause bits */ #define CBE_CAUSE_RI … #define CBE_CAUSE_INVALID_INSTRUCTION … #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN … #define CBE_CAUSE_PE_CHECK_DATA_ERROR … #define CBE_CAUSE_IAA_GAA_MISMATCH … #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION … #define CBE_CAUSE_OS_FATAL_TLB_FAULT … #define CBE_CAUSE_EXECUTION_HW_ERROR … #define CBE_CAUSE_TLBHW_ERROR … #define CBE_CAUSE_RA_REQUEST_TIMEOUT … #define CBE_CAUSE_HA_REQUEST_TIMEOUT … #define CBE_CAUSE_RA_RESPONSE_FATAL … #define CBE_CAUSE_RA_RESPONSE_NON_FATAL … #define CBE_CAUSE_HA_RESPONSE_FATAL … #define CBE_CAUSE_HA_RESPONSE_NON_FATAL … #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR … #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR … #define CBE_CAUSE_RA_RESPONSE_DATA_ERROR … #define CBE_CAUSE_HA_RESPONSE_DATA_ERROR … #define CBE_CAUSE_FORCED_ERROR … /* CBE cbrexecstatus bits */ #define CBR_EXS_ABORT_OCC_BIT … #define CBR_EXS_INT_OCC_BIT … #define CBR_EXS_PENDING_BIT … #define CBR_EXS_QUEUED_BIT … #define CBR_EXS_TLB_INVAL_BIT … #define CBR_EXS_EXCEPTION_BIT … #define CBR_EXS_CB_INT_PENDING_BIT … #define CBR_EXS_ABORT_OCC … #define CBR_EXS_INT_OCC … #define CBR_EXS_PENDING … #define CBR_EXS_QUEUED … #define CBR_EXS_TLB_INVAL … #define CBR_EXS_EXCEPTION … #define CBR_EXS_CB_INT_PENDING … /* * Exceptions are retried for the following cases. If any OTHER bits are set * in ecause, the exception is not retryable. */ #define EXCEPTION_RETRY_BITS … /* Message queue head structure */ gru_mesqhead; /* Generate the low word of a GRU instruction */ static inline unsigned long __opdword(unsigned char opcode, unsigned char exopc, unsigned char xtype, unsigned char iaa0, unsigned char iaa1, unsigned long idef2, unsigned char ima) { … } /* * Architecture specific intrinsics */ static inline void gru_flush_cache(void *p) { … } /* * Store the lower 64 bits of the command including the "start" bit. Then * start the instruction executing. */ static inline void gru_start_instruction(struct gru_instruction *ins, unsigned long op64) { … } /* Convert "hints" to IMA */ #define CB_IMA(h) … /* Convert data segment cache line index into TRI0 / TRI1 value */ #define GRU_DINDEX(i) … /* Inline functions for GRU instructions. * Note: * - nelem and stride are in elements * - tri0/tri1 is in bytes for the beginning of the data segment. */ static inline void gru_vload_phys(void *cb, unsigned long gpa, unsigned int tri0, int iaa, unsigned long hints) { … } static inline void gru_vstore_phys(void *cb, unsigned long gpa, unsigned int tri0, int iaa, unsigned long hints) { … } static inline void gru_vload(void *cb, unsigned long mem_addr, unsigned int tri0, unsigned char xtype, unsigned long nelem, unsigned long stride, unsigned long hints) { … } static inline void gru_vstore(void *cb, unsigned long mem_addr, unsigned int tri0, unsigned char xtype, unsigned long nelem, unsigned long stride, unsigned long hints) { … } static inline void gru_ivload(void *cb, unsigned long mem_addr, unsigned int tri0, unsigned int tri1, unsigned char xtype, unsigned long nelem, unsigned long hints) { … } static inline void gru_ivstore(void *cb, unsigned long mem_addr, unsigned int tri0, unsigned int tri1, unsigned char xtype, unsigned long nelem, unsigned long hints) { … } static inline void gru_vset(void *cb, unsigned long mem_addr, unsigned long value, unsigned char xtype, unsigned long nelem, unsigned long stride, unsigned long hints) { … } static inline void gru_ivset(void *cb, unsigned long mem_addr, unsigned int tri1, unsigned long value, unsigned char xtype, unsigned long nelem, unsigned long hints) { … } static inline void gru_vflush(void *cb, unsigned long mem_addr, unsigned long nelem, unsigned char xtype, unsigned long stride, unsigned long hints) { … } static inline void gru_nop(void *cb, int hints) { … } static inline void gru_bcopy(void *cb, const unsigned long src, unsigned long dest, unsigned int tri0, unsigned int xtype, unsigned long nelem, unsigned int bufsize, unsigned long hints) { … } static inline void gru_bstore(void *cb, const unsigned long src, unsigned long dest, unsigned int tri0, unsigned int xtype, unsigned long nelem, unsigned long hints) { … } static inline void gru_gamir(void *cb, int exopc, unsigned long src, unsigned int xtype, unsigned long hints) { … } static inline void gru_gamirr(void *cb, int exopc, unsigned long src, unsigned int xtype, unsigned long hints) { … } static inline void gru_gamer(void *cb, int exopc, unsigned long src, unsigned int xtype, unsigned long operand1, unsigned long operand2, unsigned long hints) { … } static inline void gru_gamerr(void *cb, int exopc, unsigned long src, unsigned int xtype, unsigned long operand1, unsigned long operand2, unsigned long hints) { … } static inline void gru_gamxr(void *cb, unsigned long src, unsigned int tri0, unsigned long hints) { … } static inline void gru_mesq(void *cb, unsigned long queue, unsigned long tri0, unsigned long nelem, unsigned long hints) { … } static inline unsigned long gru_get_amo_value(void *cb) { … } static inline int gru_get_amo_value_head(void *cb) { … } static inline int gru_get_amo_value_limit(void *cb) { … } static inline union gru_mesqhead gru_mesq_head(int head, int limit) { … } /* * Get struct control_block_extended_exc_detail for CB. */ extern int gru_get_cb_exception_detail(void *cb, struct control_block_extended_exc_detail *excdet); #define GRU_EXC_STR_SIZE … /* * Control block definition for checking status */ struct gru_control_block_status { … }; /* Get CB status */ static inline int gru_get_cb_status(void *cb) { … } /* Get CB message queue substatus */ static inline int gru_get_cb_message_queue_substatus(void *cb) { … } /* Get CB substatus */ static inline int gru_get_cb_substatus(void *cb) { … } /* * User interface to check an instruction status. UPM and exceptions * are handled automatically. However, this function does NOT wait * for an active instruction to complete. * */ static inline int gru_check_status(void *cb) { … } /* * User interface (via inline function) to wait for an instruction * to complete. Completion status (IDLE or EXCEPTION is returned * to the user. Exception due to hardware errors are automatically * retried before returning an exception. * */ static inline int gru_wait(void *cb) { … } /* * Wait for CB to complete. Aborts program if error. (Note: error does NOT * mean TLB mis - only fatal errors such as memory parity error or user * bugs will cause termination. */ static inline void gru_wait_abort(void *cb) { … } /* * Get a pointer to the start of a gseg * p - Any valid pointer within the gseg */ static inline void *gru_get_gseg_pointer (void *p) { … } /* * Get a pointer to a control block * gseg - GSeg address returned from gru_get_thread_gru_segment() * index - index of desired CB */ static inline void *gru_get_cb_pointer(void *gseg, int index) { … } /* * Get a pointer to a cacheline in the data segment portion of a GSeg * gseg - GSeg address returned from gru_get_thread_gru_segment() * index - index of desired cache line */ static inline void *gru_get_data_pointer(void *gseg, int index) { … } /* * Convert a vaddr into the tri index within the GSEG * vaddr - virtual address of within gseg */ static inline int gru_get_tri(void *vaddr) { … } #endif /* __GRU_INSTRUCTIONS_H__ */
Codebase Browser
linux