/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __GENWQE_CARD_H__ #define __GENWQE_CARD_H__ /** * IBM Accelerator Family 'GenWQE' * * (C) Copyright IBM Corp. 2013 * * Author: Frank Haverkamp <[email protected]> * Author: Joerg-Stephan Vogt <[email protected]> * Author: Michael Jung <[email protected]> * Author: Michael Ruettger <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License (version 2 only) * as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /* * User-space API for the GenWQE card. For debugging and test purposes * the register addresses are included here too. */ #include <linux/types.h> #include <linux/ioctl.h> /* Basename of sysfs, debugfs and /dev interfaces */ #define GENWQE_DEVNAME … #define GENWQE_TYPE_ALTERA_230 … #define GENWQE_TYPE_ALTERA_530 … #define GENWQE_TYPE_ALTERA_A4 … #define GENWQE_TYPE_ALTERA_A7 … /* MMIO Unit offsets: Each UnitID occupies a defined address range */ #define GENWQE_UID_OFFS(uid) … #define GENWQE_SLU_OFFS … #define GENWQE_HSU_OFFS … #define GENWQE_APP_OFFS … #define GENWQE_MAX_UNITS … /* Common offsets per UnitID */ #define IO_EXTENDED_ERROR_POINTER … #define IO_ERROR_INJECT_SELECTOR … #define IO_EXTENDED_DIAG_SELECTOR … #define IO_EXTENDED_DIAG_READ_MBX … #define IO_EXTENDED_DIAG_MAP(ring) … #define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) … /* UnitID 0: Service Layer Unit (SLU) */ /* SLU: Unit Configuration Register */ #define IO_SLU_UNITCFG … #define IO_SLU_UNITCFG_TYPE_MASK … /* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */ #define IO_SLU_FIR … #define IO_SLU_FIR_CLR … /* SLU: First Error Capture Register (FEC/WOF) */ #define IO_SLU_FEC … #define IO_SLU_ERR_ACT_MASK … #define IO_SLU_ERR_ATTN_MASK … #define IO_SLU_FIRX1_ACT_MASK … #define IO_SLU_FIRX0_ACT_MASK … #define IO_SLU_SEC_LEM_DEBUG_OVR … #define IO_SLU_EXTENDED_ERR_PTR … #define IO_SLU_COMMON_CONFIG … #define IO_SLU_FLASH_FIR … #define IO_SLU_SLC_FIR … #define IO_SLU_RIU_TRAP … #define IO_SLU_FLASH_FEC … #define IO_SLU_SLC_FEC … /* * The Virtual Function's Access is from offset 0x00010000 * The Physical Function's Access is from offset 0x00050000 * Single Shared Registers exists only at offset 0x00060000 * * SLC: Queue Virtual Window Window for accessing into a specific VF * queue. When accessing the 0x10000 space using the 0x50000 address * segment, the value indicated here is used to specify which VF * register is decoded. This register, and the 0x50000 register space * can only be accessed by the PF. Example, if this register is set to * 0x2, then a read from 0x50000 is the same as a read from 0x10000 * from VF=2. */ /* SLC: Queue Segment */ #define IO_SLC_QUEUE_SEGMENT … #define IO_SLC_VF_QUEUE_SEGMENT … /* SLC: Queue Offset */ #define IO_SLC_QUEUE_OFFSET … #define IO_SLC_VF_QUEUE_OFFSET … /* SLC: Queue Configuration */ #define IO_SLC_QUEUE_CONFIG … #define IO_SLC_VF_QUEUE_CONFIG … /* SLC: Job Timout/Only accessible for the PF */ #define IO_SLC_APPJOB_TIMEOUT … #define IO_SLC_VF_APPJOB_TIMEOUT … #define TIMEOUT_250MS … #define HEARTBEAT_DISABLE … /* SLC: Queue InitSequence Register */ #define IO_SLC_QUEUE_INITSQN … #define IO_SLC_VF_QUEUE_INITSQN … /* SLC: Queue Wrap */ #define IO_SLC_QUEUE_WRAP … #define IO_SLC_VF_QUEUE_WRAP … /* SLC: Queue Status */ #define IO_SLC_QUEUE_STATUS … #define IO_SLC_VF_QUEUE_STATUS … /* SLC: Queue Working Time */ #define IO_SLC_QUEUE_WTIME … #define IO_SLC_VF_QUEUE_WTIME … /* SLC: Queue Error Counts */ #define IO_SLC_QUEUE_ERRCNTS … #define IO_SLC_VF_QUEUE_ERRCNTS … /* SLC: Queue Loast Response Word */ #define IO_SLC_QUEUE_LRW … #define IO_SLC_VF_QUEUE_LRW … /* SLC: Freerunning Timer */ #define IO_SLC_FREE_RUNNING_TIMER … #define IO_SLC_VF_FREE_RUNNING_TIMER … /* SLC: Queue Virtual Access Region */ #define IO_PF_SLC_VIRTUAL_REGION … /* SLC: Queue Virtual Window */ #define IO_PF_SLC_VIRTUAL_WINDOW … /* SLC: DDCB Application Job Pending [n] (n=0:63) */ #define IO_PF_SLC_JOBPEND(n) … #define IO_SLC_JOBPEND(n) … /* SLC: Parser Trap RAM [n] (n=0:31) */ #define IO_SLU_SLC_PARSE_TRAP(n) … /* SLC: Dispatcher Trap RAM [n] (n=0:31) */ #define IO_SLU_SLC_DISP_TRAP(n) … /* Global Fault Isolation Register (GFIR) */ #define IO_SLC_CFGREG_GFIR … #define GFIR_ERR_TRIGGER … /* SLU: Soft Reset Register */ #define IO_SLC_CFGREG_SOFTRESET … /* SLU: Misc Debug Register */ #define IO_SLC_MISC_DEBUG … #define IO_SLC_MISC_DEBUG_CLR … #define IO_SLC_MISC_DEBUG_SET … /* Temperature Sensor Reading */ #define IO_SLU_TEMPERATURE_SENSOR … #define IO_SLU_TEMPERATURE_CONFIG … /* Voltage Margining Control */ #define IO_SLU_VOLTAGE_CONTROL … #define IO_SLU_VOLTAGE_NOMINAL … #define IO_SLU_VOLTAGE_DOWN5 … #define IO_SLU_VOLTAGE_UP5 … /* Direct LED Control Register */ #define IO_SLU_LEDCONTROL … /* SLU: Flashbus Direct Access -A5 */ #define IO_SLU_FLASH_DIRECTACCESS … /* SLU: Flashbus Direct Access2 -A5 */ #define IO_SLU_FLASH_DIRECTACCESS2 … /* SLU: Flashbus Command Interface -A5 */ #define IO_SLU_FLASH_CMDINTF … /* SLU: BitStream Loaded */ #define IO_SLU_BITSTREAM … /* This Register has a switch which will change the CAs to UR */ #define IO_HSU_ERR_BEHAVIOR … #define IO_SLC2_SQB_TRAP … #define IO_SLC2_QUEUE_MANAGER_TRAP … #define IO_SLC2_FLS_MASTER_TRAP … /* UnitID 1: HSU Registers */ #define IO_HSU_UNITCFG … #define IO_HSU_FIR … #define IO_HSU_FIR_CLR … #define IO_HSU_FEC … #define IO_HSU_ERR_ACT_MASK … #define IO_HSU_ERR_ATTN_MASK … #define IO_HSU_FIRX1_ACT_MASK … #define IO_HSU_FIRX0_ACT_MASK … #define IO_HSU_SEC_LEM_DEBUG_OVR … #define IO_HSU_EXTENDED_ERR_PTR … #define IO_HSU_COMMON_CONFIG … /* UnitID 2: Application Unit (APP) */ #define IO_APP_UNITCFG … #define IO_APP_FIR … #define IO_APP_FIR_CLR … #define IO_APP_FEC … #define IO_APP_ERR_ACT_MASK … #define IO_APP_ERR_ATTN_MASK … #define IO_APP_FIRX1_ACT_MASK … #define IO_APP_FIRX0_ACT_MASK … #define IO_APP_SEC_LEM_DEBUG_OVR … #define IO_APP_EXTENDED_ERR_PTR … #define IO_APP_COMMON_CONFIG … #define IO_APP_DEBUG_REG_01 … #define IO_APP_DEBUG_REG_02 … #define IO_APP_DEBUG_REG_03 … #define IO_APP_DEBUG_REG_04 … #define IO_APP_DEBUG_REG_05 … #define IO_APP_DEBUG_REG_06 … #define IO_APP_DEBUG_REG_07 … #define IO_APP_DEBUG_REG_08 … #define IO_APP_DEBUG_REG_09 … #define IO_APP_DEBUG_REG_10 … #define IO_APP_DEBUG_REG_11 … #define IO_APP_DEBUG_REG_12 … #define IO_APP_DEBUG_REG_13 … #define IO_APP_DEBUG_REG_14 … #define IO_APP_DEBUG_REG_15 … #define IO_APP_DEBUG_REG_16 … #define IO_APP_DEBUG_REG_17 … #define IO_APP_DEBUG_REG_18 … /* Read/write from/to registers */ struct genwqe_reg_io { … }; /* * All registers of our card will return values not equal this values. * If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the * card can be considered as unusable. It will need recovery. */ #define IO_ILLEGAL_VALUE … /* * Generic DDCB execution interface. * * This interface is a first prototype resulting from discussions we * had with other teams which wanted to use the Genwqe card. It allows * to issue a DDCB request in a generic way. The request will block * until it finishes or time out with error. * * Some DDCBs require DMA addresses to be specified in the ASIV * block. The interface provies the capability to let the kernel * driver know where those addresses are by specifying the ATS field, * such that it can replace the user-space addresses with appropriate * DMA addresses or DMA addresses of a scatter gather list which is * dynamically created. * * Our hardware will refuse DDCB execution if the ATS field is not as * expected. That means the DDCB execution engine in the chip knows * where it expects DMA addresses within the ASIV part of the DDCB and * will check that against the ATS field definition. Any invalid or * unknown ATS content will lead to DDCB refusal. */ /* Genwqe chip Units */ #define DDCB_ACFUNC_SLU … #define DDCB_ACFUNC_APP … /* DDCB return codes (RETC) */ #define DDCB_RETC_IDLE … #define DDCB_RETC_PENDING … #define DDCB_RETC_COMPLETE … #define DDCB_RETC_FAULT … #define DDCB_RETC_ERROR … #define DDCB_RETC_FORCED_ERROR … #define DDCB_RETC_UNEXEC … #define DDCB_RETC_TERM … #define DDCB_RETC_RES0 … #define DDCB_RETC_RES1 … /* DDCB Command Options (CMDOPT) */ #define DDCB_OPT_ECHO_FORCE_NO … #define DDCB_OPT_ECHO_FORCE_102 … #define DDCB_OPT_ECHO_FORCE_104 … #define DDCB_OPT_ECHO_FORCE_108 … #define DDCB_OPT_ECHO_FORCE_110 … #define DDCB_OPT_ECHO_FORCE_120 … #define DDCB_OPT_ECHO_FORCE_140 … #define DDCB_OPT_ECHO_FORCE_180 … #define DDCB_OPT_ECHO_COPY_NONE … #define DDCB_OPT_ECHO_COPY_ALL … /* Definitions of Service Layer Commands */ #define SLCMD_ECHO_SYNC … #define SLCMD_MOVE_FLASH … #define SLCMD_MOVE_FLASH_FLAGS_MODE … #define SLCMD_MOVE_FLASH_FLAGS_DLOAD … #define SLCMD_MOVE_FLASH_FLAGS_EMUL … #define SLCMD_MOVE_FLASH_FLAGS_UPLOAD … #define SLCMD_MOVE_FLASH_FLAGS_VERIFY … #define SLCMD_MOVE_FLASH_FLAG_NOTAP … #define SLCMD_MOVE_FLASH_FLAG_POLL … #define SLCMD_MOVE_FLASH_FLAG_PARTITION … #define SLCMD_MOVE_FLASH_FLAG_ERASE … enum genwqe_card_state { … }; /* common struct for chip image exchange */ struct genwqe_bitstream { … }; /* Issuing a specific DDCB command */ #define DDCB_LENGTH … #define DDCB_ASIV_LENGTH … #define DDCB_ASIV_LENGTH_ATS … #define DDCB_ASV_LENGTH … #define DDCB_FIXUPS … struct genwqe_debug_data { … }; /* * Address Translation Specification (ATS) definitions * * Each 4 bit within the ATS 64-bit word specify the required address * translation at the defined offset. * * 63 LSB * 6666.5555.5555.5544.4444.4443.3333.3333 ... 11 * 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210 * * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78 * res res res res ASIV ... * The first 4 entries in the ATS word are reserved. The following nibbles * each describe at an 8 byte offset the format of the required data. */ #define ATS_TYPE_DATA … #define ATS_TYPE_FLAT_RD … #define ATS_TYPE_FLAT_RDWR … #define ATS_TYPE_SGL_RD … #define ATS_TYPE_SGL_RDWR … #define ATS_SET_FLAGS(_struct, _field, _flags) … #define ATS_GET_FLAGS(_ats, _byte_offs) … /** * struct genwqe_ddcb_cmd - User parameter for generic DDCB commands * * On the way into the kernel the driver will read the whole data * structure. On the way out the driver will not copy the ASIV data * back to user-space. */ struct genwqe_ddcb_cmd { … }; #define GENWQE_IOC_CODE … /* Access functions */ #define GENWQE_READ_REG64 … #define GENWQE_WRITE_REG64 … #define GENWQE_READ_REG32 … #define GENWQE_WRITE_REG32 … #define GENWQE_READ_REG16 … #define GENWQE_WRITE_REG16 … #define GENWQE_GET_CARD_STATE … /** * struct genwqe_mem - Memory pinning/unpinning information * @addr: virtual user space address * @size: size of the area pin/dma-map/unmap * direction: 0: read/1: read and write * * Avoid pinning and unpinning of memory pages dynamically. Instead * the idea is to pin the whole buffer space required for DDCB * opertionas in advance. The driver will reuse this pinning and the * memory associated with it to setup the sglists for the DDCB * requests without the need to allocate and free memory or map and * unmap to get the DMA addresses. * * The inverse operation needs to be called after the pinning is not * needed anymore. The pinnings else the pinnings will get removed * after the device is closed. Note that pinnings will required * memory. */ struct genwqe_mem { … }; #define GENWQE_PIN_MEM … #define GENWQE_UNPIN_MEM … /* * Generic synchronous DDCB execution interface. * Synchronously execute a DDCB. * * Return: 0 on success or negative error code. * -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups * no mappings found/could not create mappings * -EFAULT: illegal addresses in fixups, purging failed * -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE */ #define GENWQE_EXECUTE_DDCB … #define GENWQE_EXECUTE_RAW_DDCB … /* Service Layer functions (PF only) */ #define GENWQE_SLU_UPDATE … #define GENWQE_SLU_READ … #endif /* __GENWQE_CARD_H__ */
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